Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2001-02-07
2003-04-01
Abraham, Fetsum (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S751000, C257S754000, C257S755000, C257S758000
Reexamination Certificate
active
06541866
ABSTRACT:
RELATED APPLICATIONS
This application contains subject matter similar to subject matter disclosed in copending U.S. patent applications Ser. No. 09/731,006 filed on Dec. 7, 2000, Ser. No. 09/031,026 filed on Dec. 7, 2000 and Ser. No. 09/731,024 filed on Dec. 7, 2000.
TECHNICAL FIELD
The present invention relates to the fabrication of semiconductor devices, particularly to self-aligned silicide (salicide) technology, and the resulting devices. The present invention is particularly applicable to ultra large scale integrated circuit (ULSI) systems having features in the deep sub-micron regime.
BACKGROUND ART
As integrated circuit geometries continue to plunge into the deep sub-micron regime, it becomes increasingly more difficult to accurately form discrete devices on a semiconductor substrate with the requisite reliability. High performance microprocessor applications require rapid speed of semiconductor circuitry. The speed of semiconductor circuitry varies inversely with the resistance (R) and capacitance (C) of the interconnection system. The higher the value of the R×C product, the more limiting the circuit operating speed. Miniaturization requires long interconnects having small contacts and small cross-sections. Accordingly, continuing reduction in design rules into the deep sub-micron regime requires decreasing the R and C associated with interconnection paths. Thus, low resistivity interconnection paths are critical to fabricate dense, high performance devices.
A common approach to reduce the resistivity of the interconnect to less than that exhibited by polycrystalline silicon alone, e.g., less than about 15-300 ohm/sq, comprises forming a multilayer structure consisting of a low resistance material, e.g., a refractory metal silicide, on top of a doped polycrystalline silicon layer, typically referred to as a polycide. Advantageously, the polycide gate/interconnect structure preserves the known work function of polycrystalline silicon and the highly reliable polycrystalline silicon/silicon oxide interface, since polycrystalline silicon is directly on top of the gate oxide.
Various metal silicides have been employed in salicide technology, such as cobalt, tungsten, and cobalt. Nickel, however, offers particular advantages vis-à-vis other metals in salicide technology. Nickel requires a lower thermal budget in that nickel silicide can be formed in a single heating step at a relatively low temperature of about 250° C. to about 600° C. with an attendant reduction in consumption of silicon in the substrate, thereby enabling the formation of ultra shallow source/drain junctions.
In conventional salicide technology, a layer of the metal is deposited on the gate electrode and on the exposed surfaces of the source/drain regions, followed by heating to react the deposited metal with underlying silicon to form the metal silicide. Unreacted metal is then removed from the dielectric sidewall spacers leaving metal silicide contacts on the upper surface of the gate electrode and on the source/drain regions. However, as device geometries continue to shrink and the height and width of gate electrodes are reduced, it was found increasingly difficult to control nickel silicidation of a silicon gate electrode, e.g., a polycrystalline silicon gate electrode. As nickel is highly reactive and diffusive, it was found difficult to prevent complete nickel silicidation of small sized polycrystalline silicon gate electrodes. A completely silicidized gate electrode is undesirable in that the known work function of polycrystalline silicon and the highly reliable polycrystalline silicon/silicon oxide interface would not be preserved. Moreover, upon complete silicidation of the gate electrode, penetration of nickel through the thin underlying gate insulating film would occur.
Accordingly, there exists a need for nickel silicidation technology in forming a polycide structure with controlled formation of nickel silicide on the gate electrode.
DISCLOSURE OF THE INVENTION
An advantage of the present invention is a semiconductor device exhibiting reduced parasitic RC time delays and containing transistors with polycide structures of polycrystalline silicon and nickel silicide.
Another advantage of the present invention is a method of manufacturing a semiconductor device exhibiting reduced parasitic RC time delays and containing transistors with polycide gate electrodes comprising polycrystalline silicon and nickel silicide.
Additional advantages and other features of the present invention will be set forth in the description which follows and in part will be apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved, in part, by a semiconductor device comprising: a silicon (Si)-containing substrate; a gate insulating layer on the substrate; and a transistor gate electrode, having opposing side surfaces, on the gate insulating layer, the gate electrode comprising: a layer of Si; a layer of cobalt silicide on the Si layer; and a layer of nickel silicide on the cobalt silicide layer.
Another advantage of the present invention is a method of manufacturing a semiconductor device, the method comprising: forming a gate insulating layer on a silicon (Si)-containing semiconductor substrate; depositing a first layer of Si on the gate insulating layer; depositing a layer of cobalt (Co) on the first Si layer; depositing a second Si layer on the Co layer; and patterning the second Si layer, Co layer, first Si layer and gate insulating layer to form a transistor gate electrode structure having an upper surface and opposing side surfaces.
Embodiments of the present invention include forming an oxide liner, as at a thickness of about 130 Å to about 170 Å, on the side surfaces of the gate electrode, and then forming silicon nitride sidewall spacers, as at a thickness of about 850 Å to about 950 Å, on the oxide liner. The first and second silicon layers, such as polycrystalline silicon, can be deposited at similar heights, and the cobalt layer, which can be deposited by physical vapor deposition (PVD) e.g., sputtering, or chemical vapor deposition (CVD), can be deposited at a thickness of about 10 Å to about 50 Å. The nickel layer is then deposited, as at a thickness of about 150 Å to about 500 Å, e.g., about 300 Å. Upon heating at a temperature of about 250° C. to about 600° C., e.g., about 400° C. to about 600° C., the deposited nickel reacts with underlying silicon in the second polycrystalline silicon layer to form nickel silicide. However, silicidation of the first polycrystalline silicon layer is substantially prevented by the formation of a cobalt silicide layer thereon.
Additional advantages of the present invention will become readily apparent to those skilled in the this art from the following detailed description, wherein embodiments of the present invention are described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
REFERENCES:
patent: 6015748 (2000-01-01), Kim et al.
patent: 6368956 (2002-04-01), Totori
Bertrand Jacques J.
Kluth George J.
Mei-Chu Woo Christy
Ngo Minh Van
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