Coaxial clock tree for programmable logic devices

Details Coaxial clock tree for programmable logic devices Coaxial clock tree for programmable logic devices

2006-02-14

2006-02-14

Tran, Anh Q. (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C326S041000, C326S047000, C326S101000

Reexamination Certificate

active

06998876

ABSTRACT:
A balanced clock tree has a coaxial structure when a piece of the tree is viewed in cross-section. A plate is capacitively coupled to the inner conductor that runs down the center of the coaxial structure. This plate is usable to AC couple into the clock signal being propagated down the clock line. A programmable structure is disclosed for doing this whereby the clock signal is capacitively coupled from the clock line onto the input lead of a latch. The latch recreates the clock signal. The latch drives the recreated clock signal onto a local clock conductor. The structure is programmable in that it either couples the clock signal onto the local conductor or not depending on the state of a configuration bit in a memory cell of the programmable structure. In one embodiment, the clock tree can be tapped without substantially affecting signal propagation characteristics of the clock tree.

REFERENCES:
patent: 6879185 (2005-04-01), Swami et al.
patent: 2001/0000426 (2001-04-01), Sung et al.
U.S. Appl. No. 10/633,727, filed Aug. 04, 2003, Conn et al.

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