CMP uniformity

Details CMP uniformity CMP uniformity

2000-01-24

2001-06-19

Hail, III, Joseph J. (Department: 3723)

Abrading

Machine

Rotary tool

C451S057000

Reexamination Certificate

active

06248006

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method and apparatus that provide uniform polishing when applying the process of Chemical Mechanical Polishing to the surface of a semiconductor wafer.
(2) Description of the Prior Art
The present invention relates to the technology of polishing or planarizing semiconductor surfaces including substrate surfaces during or after the process of processing these surfaces. The creation of semiconductor surfaces typically includes the creation of active devices in the surface of the substrates, the polishing of semiconductor surfaces can occur at any time within the sequence of processing semiconductors where such an operation of polishing is beneficial or deemed necessary.
That good surface planarity during the creation of semiconductor devices is of prime importance in achieving satisfactory product yield and in maintaining target product costs is readily evident in light of the fact that a semiconductor device typically contains a multiplicity of layers that form a structure of one or more layers superimposed over one or more layers. Any layer within that structure that does not have good planarity leads to problems of increased severity for the overlying layers. Most of the processing steps that are performed in creating a semiconductor device involve steps of photolithography that critically depend on being able to sharply define device features, a requirement that becomes increasingly more important where device features are in the sub-micron range or even smaller, down to about 0.1 um. Planarity directly affects the impact that light has on the surface of for instance a layer of photoresist, a layer which is typically used for patterning and etching the various layers that make up a semiconductor device. Lack of planarity leads to light diffusion which leads to poor depth of focus and a limitation on feature resolution (features such as adjacent lines cannot be closely spaced, a key requirement in today's manufacturing environment). This requirement, although of a general nature, can take on special stringency dependent on the material, for instance a relatively frequently used metal such as copper, that is being polished. Copper, typically applied using the damascene process for the creation of conductive lines and vias, is one of the most promising technologies to reduce RC delay as well as to implement the shrinkage of metal interconnect line structures. Damascene is an interconnection fabrication process in which grooves are formed in an insulating layer and filled with metal to form the conductive lines. Dual damascene is a multi-level interconnection process in which, in-addition to forming the grooves of single damascene, conductive via openings also are formed. For this, Chemical Mechanical Polishing (CMP) of inlaid copper is required to form the copper wiring. One of the major problems that is encountered when polishing inlaid copper patterns is the damage that is caused on the copper trench as a consequence of the polishing process.
Chemical Mechanical Polishing (CMP) is a method of polishing materials, such as semiconductor substrates, to a high degree of planarity and uniformity. The process is used to planarize semiconductor slices prior to the fabrication of semiconductor circuitry thereon, and is also used to remove high elevation features created during the fabrication of the microelectronic circuitry on the substrate. One typical chemical mechanical polishing process uses a large polishing pad that is located on a rotating platen against which a substrate is positioned for polishing, and a positioning member which positions and biases the substrate on the rotating polishing pad. Chemical slurry, which may also include abrasive materials, is maintained on the polishing pad to modify the polishing characteristics of the polishing pad in order to enhance the polishing of the substrate.
While copper has become important for the creation of multilevel interconnections, copper lines frequently show damage after CMP and clean. This in turn causes problems with planarization of subsequent layers that are deposited over the copper lines since these layers may now be deposited on a surface of poor planarity. Isolated copper lines or copper lines that are adjacent to open fields are susceptible to damage. While the root causes for these damages are at this time not clearly understood, poor copper gap fill together with subsequent problems of etching and planarization are suspected. Where over-polish is required, the problem of damaged copper lines becomes even more severe.
During the Chemical Mechanical Planarization (CMP) process, semiconductor substrates are rotated, face down, against a polishing pad in the presence of abrasive slurry. Most commonly, the layer to be planarized is an electrical insulating layer overlaying active circuit devices. As the substrate is rotated against the polishing pad, the abrasive force grinds away the surface of the insulating layer. Additionally, chemical compounds within the slurry undergo a chemical reaction with the components of the insulating layer to enhance the rate of removal. By carefully selecting the chemical components of the slurry, the polishing process can be made more selective to one type of material than to another. For example, in the presence of potassium hydroxide, silicon dioxide is removed at a faster rate than silicon nitride. The ability to control the selectivity of a CMP process has led to its increased use in the fabrication of complex integrated circuits.
It is well known in the art that, in the evolution of integrated circuit chips, the process of scaling down feature size results in making device performance more heavily dependent on the interconnections between devices. In addition, the area required to route the interconnect lines becomes large relative to the area occupied by the devices. This normally leads to integrated circuit chips with multilevel levels of interconnect lines. The chips are often mounted on multi-chip modules that contain buried wiring patterns to conduct electrical signals between the various chips. These modules usually contain multiple layers of interconnect metallization separated by alternating layers of an isolating dielectric. Any conductor material that is used in a multilevel interconnect has to satisfy certain essential requirements such as low resistivity, resistance to electromigration, adhesion to the underlying substrate material, stability (both electrical and mechanical) and ease of processing.
FIG. 1
shows a Prior Art CMP apparatus. A polishing pad
20
is attached to a circular polishing table
22
that rotates in a direction indicated by arrow
24
at a rate in the order of 1 to 100 RPM. A wafer carrier
26
is used to hold wafer
18
facedown against the polishing pad
20
. The wafer
18
is held in place by applying a vacuum to the backside of the wafer (not shown). The wafer
18
can also be attached to the wafer carrier
26
by the application of a substrate attachment film (not shown) to the lower surface of the wafer carrier
26
. Slurry
23
is supplied to the surface of the wafer
20
that is being polished. The wafer carrier
26
also rotates as indicated by arrow
32
, usually in the same direction as the polishing table
22
, at a rate on the order of 1 to 100 RPM. Due to the rotation of the polishing table
22
, the wafer
18
traverses a circular polishing path over the polishing pad
20
. A force
28
is also applied in the downward vertical direction against wafer
18
and presses the wafer
18
against the polishing pad
20
as it is being polished. The force
28
is typically in the order of 0 to 15 pounds per square inch and is applied by means of a shaft
30
that is attached to the back of wafer carrier
26
.
A typical CMP process involves the use of a polishing pad made from a synthetic fabric and a polishing slurry, which includes pH-balanced chemicals, such as sodium hydroxide, an

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