Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
2000-06-19
2002-04-30
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C438S926000, C438S691000, C438S687000, C438S637000, C438S627000, C438S622000
Reexamination Certificate
active
06380087
ABSTRACT:
BACKGROUND OF THE INVENTION
Copper damascene and dual damascene structures are beginning to be used for interconnects. The damascene processing uses chemical mechanical polishing (CMP) to planarize the top surface of the copper interconnect. However dishing is a problem with CMP.
U.S. Pat. No. 5,885,856 to Gilbert et al. describes a method of forming an integrated circuit with dummy mesas added to the layout pattern of the integrated circuit to equilibrate the polishing rate across the surface of a semiconductor substrate. The location of each dummy mesa is selected to that it does not intersect a well boundary or an active region, and does not fall under a conductive layer or polysilicon or interconnect structure.
U.S. Pat. No. 5,639,687 to Weling et al. describes a method of commonizing the pattern density of topography for different layers of semiconductor wafers to improve the chemical mechanical polishing processing of the wafer. Dummy raised lines are inserted as necessary into gaps between active conductive traces on a trace layer on the wafer.
U.S. Pat. No. 5,445,994 to Gilton describes a method for forming planar metal connections to the bonding pads of a semiconductor die that can be customized to match different bonding pad and lead finger configuration
U.S. Pat. No. 5,888,889 to Frisina et al. describes a process for manufacturing an integrated structure pad assembly for wire bonding to a power semiconductor device chip.
U.S. Pat. No. 5,801,094 to Yew et al. describes a dual damascene process that forms a two level metal interconnect structure with a step free transition between the two levels.
U.S. Pat. No. 5,266,446 to Chang et al. describes a method of fabricating a planar multilayer thin film structure on the surface of a dielectric substrate by applying and first and second layer of dielectric polymeric material on a surface of a dielectric substrate. The second, upper layer of polymeric material is photosensitive and is exposed and developed to form a feature therein that is in communication with a feature in the first, lower layer of polymeric material. A seed layer is deposited over the second layer, and coating the first and second layer features. A thicker layer of conductive material is deposited over the seed layer, filling the first and second features at least to the level of the second layer, and is then planarized to remove the excess of the thicker layer.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a method of forming metal dummy plugs and active interconnects in a single etch step in a semiconductor structure.
Another object of the present invention is to provide a method of forming metal dummy plugs, in a bonding pad area, and active interconnects, in an interconnect area, in a single etch step in a interconnect area in a semiconductor structure.
A further object of the present invention is to provide a copper chemical-mechanical polishing process utilizing dummy plugs in damascene processes that minimize the erosion of the metal layer from large areas.
Yet another object of the present invention is to provide a copper chemical-mechanical polishing process utilizing dummy plugs that minimizes copper dishing during in large areas, e.g. bonding pad areas.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, semiconductor wafer structure having at least an upper and a lower dielectric layer is provided. The semiconductor wafer structure having a bonding pad area and an interconnect area. At least one active interconnect having a first width is formed in the interconnect area, through the dielectric layers. A plurality of adjacent dummy plugs each having a second width is formed in the bonding pad area, through a portion of the dielectric layers. The semiconductor wafer structure is patterned and etched to form trenches through the upper dielectric layer. The trenches surround each of the at least one active interconnect and the dummy plugs whereby the upper dielectric level between the adjacent dummy plugs is removed. A metallization layer is deposited over the lower dielectric layer, filling the trenches at least to the upper surface of the remaining upper dielectric layer. The metallization layer is planarized to remove the excess of the metallization layer forming a continuous bonding pad within the bonding pad area and including the plurality of adjacent dummy plugs, thus forming at least one damascene structure including the at least one respective active interconnect.
REFERENCES:
patent: 5266446 (1993-11-01), Chang et al.
patent: 5445994 (1995-08-01), Gilton
patent: 5459093 (1995-10-01), Kuroda et al.
patent: 5639697 (1997-06-01), Weling et al.
patent: 5801094 (1998-09-01), Yew et al.
patent: 5885856 (1999-03-01), Gilbert et al.
patent: 5888889 (1999-03-01), Frisina et al.
patent: 6016000 (2000-01-01), Moslehi
patent: 6057224 (2000-05-01), Bothra et al.
patent: 6124198 (2000-09-01), Moslehi
patent: 6232662 (2001-05-01), Saran
patent: 6251773 (2001-06-01), Hartswick et al.
Chockalingam Ramasamy
Gupta Subhash
Zhou Mei Sheng
Chartered Semiconductor Manufacturing Inc.
Everhart Caridad
Pike Rosemary L.S.
Saile George O.
Stanton Stephen G.
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