CMP-free disposable gate process

Details CMP-free disposable gate process CMP-free disposable gate process

1998-07-29

2001-05-15

Elms, Richard (Department: 2824)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257S327000

Reexamination Certificate

active

06232188

ABSTRACT:

BACKGROUND AND SUMMARY OF THE INVENTION
The present invention relates to integrated circuit structures and fabrication methods, and more specifically to forming an integrated circuit structure using a disposable gate process.
BACKGROUND: DISPOSABLE GATE PROCESS
A disposable gate process has been shown to provide a method by which a CMOS transistor structure can be scaled further into the sub-micron region while maintaining sufficiently low gate sheet resistance, small junction depth, and low junction capacitance. See provisional applications 60/029,215 filed Oct. 28, 1996 and 60/019,643 filed Oct. 28, 1996, which are hereby incorporated by reference.
A conventional disposable gate process is illustrated in
FIGS. 2A-2C
.
FIG. 2A
shows a field dielectric
114
which was blanket deposited over a disposable gate
120
(e.g. of silicon nitride) and pad oxide
122
which was formed over a semiconductor active area
102
. The field dielectric
114
is then chemically mechanically polished, leaving the surface of disposable gate
120
exposed as shown in FIG.
2
B. In
FIG. 2C
disposable gate
120
has been removed (e.g. by a hot phosphoric acid). A gate electrode can now be deposited in the space
115
left by the removal of disposable gate
120
.
The chemical mechanical polishing step (CMP) in the conventional process discussed above is a polishing technique which provides global planarization. However, CMP can be a problematic step in this conventional process because of the polish rate dependence on gate density. Yota et al.,
Integration of ICP High-Density Plasnia CVD with CMP and Its Effects on Planarity for Sub-
0.5
&mgr;m CMOS Technology
, 2875 Proceedings of the SPIE 265 (1997), which is hereby incorporated by reference. The CMP process is difficult to control because of the pattern sensitivity of the polish rate.
Background: HDP-CVD
The basic HDP-CVD (high density plasma-chemical vapor deposition) process involves a simultaneous deposition and etch component and is already well-established in the semiconductor industry. HDP-CVD can provide very non-conformal deposition, in which material buildup occurs almost complete on the flat surfaces of the starting structure, and not on sidewalls. See e.g., A. Chatterjee et al.,
A Shallow Trench Isolation Study for
0.25/0.18
&mgr;m CMOS Technologies and Beyond
, 156 Symposium on VLSI Technology Digest (1996); S. Nag et al.,
Comparative Evaluation of Gap-Fill Dielectrics in Shallow Trench Isolation for Sub-
0.25
&mgr;m Technologies
, 841 IEDM (1996), which are hereby incorporated by reference.
CMP-Free Disposable Gate Process
The present application solves the problem of polish rate dependence on gate pattern density by using a highly non-conformal field dielectric to leave the disposable gate partially exposed, thereby eliminating the need to chemically-mechanically-polish the field dielectric to expose the disposable gate. In a sample embodiment, HDP-CVD oxide is deposited non-conformally as the field oxide over a disposable gate structure. The deposition process uses a sputter component to achieve minimal deposition on the sidewalls of the disposable gate. The oxide deposition is preferably stopped before the oxide filling up the trench and the oxide depositing on top of the disposable gate meet, thus leaving the sidewalls of the disposable gate partially exposed. Optionally, a short oxide etch can be used to selectively remove any oxide which deposited on the sides of the disposable gate, thereby leaving the sidewalls of the gate partially exposed. Because the sidewalls are exposed, the process can proceed directly to selective removal of the disposable gate, rather than going through a CMP step to expose the disposable gate before removal can proceed.
Advantages of the disclosed methods and structures include:
eliminating the need for CMP after field-oxide deposition;
simplifying the overall disposable gate process;
eliminating pattern sensitivity to the degree of planarity;
high-k gate dielectrics and/or metal gates (e.g. aluminum) are not subjected to high temperatures in a disposable gate process;
limits on lateral dimensions of a disposable gate can be avoided;
a thicker disposable gate structure can be used to provide a higher margin of error;
the field oxide can provide a thicker oxide etch-stop than the gate oxide.


REFERENCES:
patent: 4845046 (1989-07-01), Shimbo
patent: 4948745 (1990-08-01), Pfiester
patent: 4963501 (1990-10-01), Ryan et al.
patent: 4992388 (1991-02-01), Pfiester
patent: 5168072 (1992-12-01), Moslehi
patent: 5322809 (1994-06-01), Moslehi
patent: 5429956 (1995-07-01), Shell et al.
patent: 5468665 (1995-11-01), Lee et al.
patent: 5496750 (1996-03-01), Moslehi
patent: 5716861 (1998-02-01), Moslehi
“Integration of ICP High-Density Plasma CVD With CMP and It's Effects on Planarity for Sub-0.5&mgr;m CMOS Technology,” SPIE vol. 2875, pp. 265-274 (Jiro Yota, Maureen R. Brongo, Thomas W. Dyer and Kenneth P. Rafftesaeth).
“Statistical Metrology for Characterizing CMP Processes,” 1997 Elsevier Science B.V., pp. 231-240 (Sharad Prasad, W. Loh, A. Kapoor, E. Chang, B. Stine, D. Boning and J. Chung).
“Chemical Mechanical Planarization of Multilayer Dielectric Stacks,” SPIE vol. 2335, pp. 2-11 (Manoj K. Jain, Girish A. Dixit, Michael F. Chisholm, Thomas R. Seha, Kelly J. Taylor, Gregory B. Shinn, and Robert H. Havemann).
“MOS Fabrication Process Integrating Self-Aligned Polysilicon Gate and Post-Processed Metal Gate Devices on a Single Die,” 1991 IEEE, pp. 199-203 (Ronald D. Butler and Robert E. Beaty).
“HDP Dielectric BEOL Gapfill: A Process for Manufacturing,” 1996 IEEE/SEMI Advanced Semiconductor Manufacturing Conference, pp. 255-258 (M.C. Broomfield and T.A. Spooner).
“Assessment of Charge-Induced Damage From High Density Plasma (HDP) Oxide Deposition,” 1996 1st International Symposium on Plasma Process-Induced Damage, May 13-14, Santa Clara, CA, 1996 American Vacuum Society, pp. 67-70 (Srikanth Krishnan and Somnath Nag).
“A Shallow Trench Isolation Study for 0.25/0.18&mgr;m CMOS Technologies and Beyond,” 1996 Symposium on VLSI Technology Digest of Technical Papers, pp. 156-157 (A. Chatterjee, J. Esquivel, S. Nag, I. Ali, D. Rogers, K. Taylor, K. Joyner, M. Mason, D. Mercer, A. Amerasekera, T. Houston and I.C. Chen).
“Comparative Evaluation of Gap-Fill Dielectrics in Shallow Trench Isolation for Sub-0.25&mgr;m Technologies,” 1996 IEEE IEDM 96-841, pp. 32.6.1-32.6.4(S. Nag, A Chatterjee, K. Taylor, I. Ali, S. O'Brien, S. Aur. J.D. Luttmer and I-C Chen).
Wolf et al., Silicon Processing for the VLSI Era, vol. 1—Process Technology, (Lattice Press, California, 1986), pp. 185-187.*
J. R. Pfiester et al, A Self-Aligned Elevated Source/Drain MOSFET, IEEE Electron Device Letters, 11 (1990) 365.

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