Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2007-05-15
2007-05-15
Crane, Sara (Department: 2811)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S221000, C438S763000
Reexamination Certificate
active
10620605
ABSTRACT:
Conventional CMOS devices suffer from imbalance because the mobility of holes in the PMOS transistor is less than the mobility of electrons in the NMOS transistor. The use of strained silicon in the channels of CMOS devices further exacerbates the difference in electron and hole mobility, as strained silicon provides a greater increase in electron mobility than hole mobility. However, hole mobility is increased in the SiGe layer underlying the strained silicon layer. Therefore, a more evenly-balanced, high-speed CMOS device is formed by including strained silicon in the NMOS transistor and not in the PMOS transistor of a CMOS device.
REFERENCES:
patent: 5759898 (1998-06-01), Ek et al.
patent: 5998807 (1999-12-01), Lustig et al.
patent: 6039803 (2000-03-01), Fitzgerald et al.
patent: 6180490 (2001-01-01), Vassiliev et al.
patent: 6207530 (2001-03-01), Hsu et al.
patent: 6214653 (2001-04-01), Chen et al.
patent: 6251751 (2001-06-01), Chu et al.
patent: 6300172 (2001-10-01), Ang et al.
patent: 6313486 (2001-11-01), Kencke et al.
patent: 6407406 (2002-06-01), Tezuka
patent: 6600170 (2003-07-01), Xiang
patent: 6703271 (2004-03-01), Yeo et al.
patent: 6724008 (2004-04-01), Fitzergald
patent: 6734527 (2004-05-01), Xiang
patent: 6900094 (2005-05-01), Hammond et al.
patent: 2001/0003269 (2001-06-01), Wu et al.
patent: 2001/0008284 (2001-07-01), Huang
patent: 2001/0016383 (2001-08-01), Chen et al.
patent: 2001/0024884 (2001-09-01), Fitzgerald
patent: 2002/0123167 (2002-09-01), Fitzgerald
Shallow Trench Isolation, “Trench Isolation,” http://courses.nus.edu.sg/course/phy/>pp. 1-4.
Hitachi America, Ltd., Semiconductor Equipment Group, “Customizable Shallow Trench Isolation,” http://www.hitachi.com/semiequipment/sti.html/>p. 1.
SNP Applications/Shallow Trench Isolation (STI), “Shallow Trench Isolation (STD),” http://www.surfaceinterface.com/snpappsSTI.html/>, pp. 1-2.
Institute of Microelectronics—Deep Submicron—Shallow Trench Isolation, “Shallow Trench Isolation Module Developmetn”, http://www.ime.org.sg/deep—trench.htm/>, pp. 1-2.
David Lammers, “MIT spinout preps commercial strained silicon”, Oct. 22, 2001, http://www.eetimes.com/story/OEG20011022S0078/>, pp. 1-5.
IBM's Strained Silicon Breakthrough Image Page, Jun. 8, 2001, http://www.research.ibm.com/resources/press/strainedsilicon/>, pp. 1-2.
Dennis Sellers, “It isn't just IBM that has ‘strained silicon’ technology”, Jun. 14, 2001, http://maccentral.macworld.com
ews/0106/14.silicon.shtml/>, pp. 1-5.
Matthew French, “Amber Wave Systems ‘strained silicon’ significant for semiconductor industry”, Aug. 6, 2001, http://www.mass.../displaydetail.asp?/>, pp. 1-3.
Richard Ball, “Strained silicon wafers boost FET speed 80 per cent at US start-up”, Electronics Weekly Archive, p. 1.
Orla Higgins, Press Release, “Amber Wave Systems Corporation Announces Availability of Breakthrough Strained Silicon Technology”, Oct. 22, 2001, pp. 1-4.
Mark A. Wolf, Pres Release, Amberwave Announces Strained Silicon Technology Available Immediately, Jun. 8, 2001, p. 1.
Advanced Micro Devices , Inc.
Crane Sara
LandOfFree
CMOS with strained silicon channel NMOS and silicon... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with CMOS with strained silicon channel NMOS and silicon..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and CMOS with strained silicon channel NMOS and silicon... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3770912