CMOS Unipolar nonvolatile memory cell

Details CMOS Unipolar nonvolatile memory cell CMOS Unipolar nonvolatile memory cell

1982-02-01

1984-09-18

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365182, G11C 1300

Patent

active

044727917

ABSTRACT:
A CMOS nonvolatile memory cell, where a multiple-dielectric P-channel device is used to provide nonvolatile information storage. An N-channel device is used to limit current (and thus power dissipation) during write operations, and two other transistors are both controlled by a single word line, to selectively connect the cell to a bit line and to a column line. Thus, a total of three connections to each cell are required. The bit and column lines of adjacent columns of cells are combined, and good density is achieved in the memory array. The operating voltages are unipolar, and the read operation enhances the written information.

REFERENCES:
patent: 4402064 (1983-08-01), Arakawa

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