CMOS transistor using high stress liner layer

Details CMOS transistor using high stress liner layer CMOS transistor using high stress liner layer

2004-05-13

2008-09-30

Nguyen, Thanh (Department: 2893)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S301000, C438S303000, C438S791000

Reexamination Certificate

active

07429517

ABSTRACT:
A MOS transistor structure comprising a gate dielectric layer (30), a gate electrode (40), and source and drain regions (70) are formed in a semiconductor substrate (10). First second and third dielectric layers (110), (120), and (130) are formed over the MOS transistor structure. The second and third dielectric structures (120), (130) are removed leaving a MOS transistor with a stressed channel region resulting in improved channel mobility characteristics.

REFERENCES:
patent: 6287951 (2001-09-01), Lucas et al.
patent: 2003/0181005 (2003-09-01), Hachimine et al.
patent: 2004/0104405 (2004-06-01), Huang et al.
patent: 2005/0048753 (2005-03-01), Schwan
Wolf et al. “Silicon Processing for the VLSI ERA”, 1986, vol. 1, pp. 191-194.

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