CMOS transistor having different PMOS and NMOS gate...

Details CMOS transistor having different PMOS and NMOS gate... CMOS transistor having different PMOS and NMOS gate...

2005-02-15

2005-02-15

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

By reaction with substrate

C438S706000, C438S745000, C438S766000, C438S778000, C438S779000

Reexamination Certificate

active

06855641

ABSTRACT:
In a CMOS semiconductor device using a silicon germanium gate and a method of fabricating the same, a gate insulating layer, a conductive electrode layer that is a seed layer, a silicon germanium electrode layer, and an amorphous conductive electrode layer are sequentially formed on a semiconductor substrate. A photolithographic process is then carried out to remove the silicon germanium electrode layer in the NMOS region, so that the silicon germanium layer is formed only in the PMOS region and is not formed in the NMOS region.

REFERENCES:
patent: 5773348 (1998-06-01), Wu
patent: 6589827 (2003-07-01), Kubo et al.
patent: 6642112 (2003-11-01), Lowe et al.
patent: 6710382 (2004-03-01), Kubo et al.
patent: 2002-043566 (2002-02-01), None
patent: WO 0161749 (2001-08-01), None

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