Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2004-12-06
2008-03-18
Lebentritt, Michael (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S197000, C438S275000, C438S287000, C438S289000, C257SE21632, C257SE21636
Reexamination Certificate
active
07344934
ABSTRACT:
A CMOS device with transistors having different gate dielectric materials and a method of manufacture thereof. An aluminum-based material is used as a gate dielectric material of a PMOS device, and a hafnium-based material is used as a gate dielectric material of an NMOS device. A thin layer of silicon a few monolayers or a sub-monolayer thick is formed over the gate dielectric materials, before forming the gates. The thin layer of silicon bonds with the gate dielectric material and pins the work function of the transistors. A gate material that may comprise a metal in one embodiment is deposited over the thin layer of silicon. A CMOS device having a symmetric Vtfor the PMOS and NMOS FETs is formed.
REFERENCES:
patent: 4432035 (1984-02-01), Hsieh et al.
patent: 4990974 (1991-02-01), Vinal
patent: 5041885 (1991-08-01), Gualandris et al.
patent: 5066995 (1991-11-01), Young et al.
patent: 5162263 (1992-11-01), Kunishima et al.
patent: 5321287 (1994-06-01), Uemura et al.
patent: 5763922 (1998-06-01), Chau
patent: 5994747 (1999-11-01), Wu
patent: 6020243 (2000-02-01), Wallace et al.
patent: 6027961 (2000-02-01), Maiti et al.
patent: 6048769 (2000-04-01), Chau
patent: 6084280 (2000-07-01), Gardner et al.
patent: 6124171 (2000-09-01), Arghavani et al.
patent: 6159782 (2000-12-01), Xiang et al.
patent: 6184072 (2001-02-01), Kaushik et al.
patent: 6225163 (2001-05-01), Bergemont
patent: 6291867 (2001-09-01), Wallace et al.
patent: 6348390 (2002-02-01), Wu
patent: 6410967 (2002-06-01), Hause et al.
patent: 6444555 (2002-09-01), Ibok
patent: 6475908 (2002-11-01), Lin et al.
patent: 6492217 (2002-12-01), Bai et al.
patent: 6528858 (2003-03-01), Yu et al.
patent: 6656764 (2003-12-01), Wang et al.
patent: 6716685 (2004-04-01), Lahaug
patent: 6720221 (2004-04-01), Ahn et al.
patent: 6740944 (2004-05-01), McElheny et al.
patent: 6852645 (2005-02-01), Colombo et al.
patent: 6897095 (2005-05-01), Adetutu et al.
patent: 6921691 (2005-07-01), Li et al.
patent: 2002/0005556 (2002-01-01), Cartier et al.
patent: 2002/0135030 (2002-09-01), Horikawa
patent: 2002/0135048 (2002-09-01), Ahn et al.
patent: 2002/0151125 (2002-10-01), Kim et al.
patent: 2002/0153573 (2002-10-01), Mogami
patent: 2003/0057432 (2003-03-01), Gardner et al.
patent: 2003/0104663 (2003-06-01), Visokay et al.
patent: 2003/0116804 (2003-06-01), Visokay et al.
patent: 2003/0137017 (2003-07-01), Hisamoto et al.
patent: 2003/0141560 (2003-07-01), Sun
patent: 2003/0219953 (2003-11-01), Mayuzumi
patent: 2004/0000695 (2004-01-01), Matsuo
patent: 2004/0005749 (2004-01-01), Choi et al.
patent: 2004/0009675 (2004-01-01), Eissa et al.
patent: 2004/0023462 (2004-02-01), Rotondaro et al.
patent: 2004/0132271 (2004-07-01), Ang et al.
patent: 2004/0217429 (2004-11-01), Lin et al.
patent: 2005/0035345 (2005-02-01), Lin et al.
patent: 2005/0064663 (2005-03-01), Saito
patent: 2005/0098839 (2005-05-01), Lee et al.
patent: 2005/0101159 (2005-05-01), Droopad
patent: 2005/0139926 (2005-06-01), Shimizu et al.
patent: 2005/0224897 (2005-10-01), Chen et al.
patent: 2005/0245019 (2005-11-01), Luo et al.
patent: 2005/0280104 (2005-12-01), Li
patent: 2006/0003507 (2006-01-01), Jung et al.
patent: 2006/0017112 (2006-01-01), Wang et al.
patent: 2006/0038236 (2006-02-01), Yamamoto
patent: 1 388 889 (2004-02-01), None
patent: 1 531 496 (2005-05-01), None
patent: 2002118175 (2002-04-01), None
patent: 2004289061 (2004-10-01), None
patent: WO 01/66832 (2001-09-01), None
patent: WO 2004/095556 (2004-11-01), None
patent: WO 2005/114718 (2005-02-01), None
patent: WO 2006/061371 (2006-06-01), None
patent: WO 2006/067107 (2006-06-01), None
Hobbs, C., et al., “Fermi Level Pinning at the PolySi/Metal Oxide Interface,”2003 Symposium on VLSI Technology Digest of Technical Papers, Jun. 2003, 2 pages.
Samavedam, S.B., et al., “Fermi Level Pinning with Sub-Monolayer MeOx and Metal Gates,” IEEE, Mar. 2003, 4 pages.
“Front End Processes,” International Technology Roadmap for Semiconductor (ITRS), 2002 Update, pp. 45-62, http://member.itrs.net/.
“HighkDielectric Materials,” Tutorial: Materials for Thin Films / Microelectronics, pp. 1-3, Sigma-Aldrich Co., St. Lois, Missouri, US, http://www.sigmaaldrich.com/Area—of—Interest/Organic—Inorganic—Chemistry/Materials—Science/Thin—Films—Microelectronics/Tutorial/Dielectric—Materials.html, downloaded Jun. 9, 2004.
Guha, S., et al., “Atomic Beam Deposition of Lanthanum- and Yttrium-Based Oxide Thin Films for Gate Dielectrics,” Applied Physics Letters, Oct. 23, 2000, vol. 77, No. 17, pp. 2710-2712, American Institute of Physics.
Muller, R.S., et al., “Device Electronics for Integrated Circuits,” Second Ed., 1986, pp. 380-385, 398-399, John Wiley & Sons, New York, NY.
Wolf, S., “Silicon Processing for the VLSI Era: vol. II—CMOS Process Integration,” 1990, pp. 432-441, Lattice Press, Sunset Beach, CA.
“Front End Processes,” The International Technology Roadmap for Semiconductors: 2003 Edition, pp. 23-25, http://member.itrs.net/.
Gannavaram, S., et al., “Low Temperature (≦800° C.) Recessed Junction Selective Silicon-Germanium Source/Drain Technology for sub-70 nm CMOS,” 2000, 4 pp., IEEE, Los Alamitos, CA.
Huang, F.-J., et al., “Schottky-Clamped NMOS Transistors Implemented in a Conventional 0.8-μm CMOS Process,” IEEE Electron Device Letters, Sep. 1998, pp. 326-328, vol. 19, No. 9, IEEE, Los Alamitos, CA.
Park, D.-G., et al., “Thermally Robust Dual-Work Function ALD-MNxMOSFETS using Conventional CMOS Process Flow,” 2004 Symposium on VLSI Technology Digest of Technical Papers, 2004, pp. 186-187, IEEE, Los Alamitos, CA.
Lin, R., et al., “An Adjustable Work Function Technology Using Mo Gate for CMOS Devices,” IEEE Electron Device Letters, Jan. 2002, pp. 49-51, vol. 23, No. 1, IEEE, Los Alamitos, CA.
Wakabayashi, H., et al., “A Dual-Metal Gate CMOS Technology Using Nitrogen-Concentration-Controlled TiNx Film,” IEEE Transactions on Electron Devices, Oct. 2001, pp. 2363-2369, vol. 48, No. 10, IEEE, Los Alamitos, CA.
Hobbs, C.C., et al., “Fermi-Level Pinning at the Polysilicon/Metal Oxide Interface—Part I,” IEEE Transactions on Electron Devices, vol. 51, No. 6, Jun. 2004, pp. 971-977.
Infineon - Technologies AG
Lebentritt Michael
Lee Kyoung
Slater & Matsil L.L.P.
LandOfFree
CMOS transistor and method of manufacture thereof does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with CMOS transistor and method of manufacture thereof, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and CMOS transistor and method of manufacture thereof will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3972366