CMOS static random access memory devices

Details CMOS static random access memory devices CMOS static random access memory devices

1998-12-22

2000-11-14

Monin, Jr., Donald L.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257385, 257903, 257390, 365156, H01L 2976, H01L 2994, H01L 31062

Patent

active

061473855

ABSTRACT:
A full CMOS SRAM cell having the capability of having a reduced aspect ratio is described. The SRAM cell includes first and second transfer transistors of n-channel types, first and second driving transistors of the n-channel types and first and second load transistors of p-channel types. Each of the transistors has source and drain regions on opposite sides of a channel region formed in a semiconductor substrate and a gate over the channel region. The cell includes a first common region defined by the drain regions of the first transfer transistor and the first driving transistor connected in series therethrough. A second common region is defined by the drain regions of the second transfer transistor and the second driving transistor connected in series therethrough. The drain region of the first load transistor is disposed adjacent to the first common region between the first and second common regions. The drain region of the second load transistor is disposed between the drain region of the first load transistor and the second common region. First and second gate electrode layers are disposed generally parallel to each other, and respectively serving as the gates of the first driving transistor and the first load transistor and as the gates of the second driving transistor and the second load transistor, wherein each of the first and second gate electrode layers is made of a conductive material of a first level. First and second interconnecting layers are each made of a conductive material of a second level different from the first level, the first interconnecting layer connecting the first common region to the drain region of the first load transistor and the second gate electrode layer, the second interconnecting layer connecting the second common region to the drain region of the second load transistor and the first gate electrode layer.

REFERENCES:
patent: 5373170 (1994-12-01), Pfiester et al.
patent: 5394358 (1995-02-01), Huang
patent: 5521860 (1996-05-01), Ohkubo
patent: 5654572 (1997-08-01), Kawase
patent: 5798551 (1998-08-01), Kikushina et al.

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