CMOS SONET/ATM receiver suitable for use with pseudo ECL and TTL

Details CMOS SONET/ATM receiver suitable for use with pseudo ECL and TTL CMOS SONET/ATM receiver suitable for use with pseudo ECL and TTL

1998-02-27

1999-05-18

Tokar, Michael

Electronic digital logic circuitry

Interface

Logic level shifting

326 68, 326 71, H03K19/0185;19/094

Patent

active

059053860

ABSTRACT:
A pulse receiver, comprising a pair of complementary symmetry metal oxide silicon (CMOS) common gate amplifiers connected between a 5 volt supply (ECL) voltage rail and an ECL ground (AGND), for receiving a pair of pulse input signals IN and INB and for providing a pair of first pulse signals, CMOS apparatus for distorting the first pulse signals, to create second pulse signals from the converter having a duty cycle having a longer low logic level interval than high logic level interval, a CMOS latch for receiving and latching the second output signals from the common gate amplifiers at logic levels compatible with circuits formed of CMOS elements, a CMOS double to single ended converter connected between a VDD voltage rail and VSS ground, for receiving the latched output signals, apparatus for providing an output signal referenced to VDD and ground from the converter.

REFERENCES:
patent: 5517148 (1996-05-01), Yin
patent: 5570042 (1996-10-01), Ma
patent: 5606268 (1997-02-01), Van Brunt
patent: 5617045 (1997-04-01), Asahina

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