Electronic digital logic circuitry – Interface – Logic level shifting
Patent
1996-01-02
1998-08-11
Westin, Edward P.
Electronic digital logic circuitry
Interface
Logic level shifting
327175, 327333, H03K 190185
Patent
active
057932255
ABSTRACT:
A pulse receiver, comprising a pair of complementary symmetry metal oxide silicon (CMOS) common gate amplifiers connected between a 5 volt supply (ECL) voltage rail and an ECL ground (AGND), for receiving a pair of pulse input signals IN and INB and for providing a pair of first pulse signals, CMOS apparatus for distorting the first pulse signals, to create second pulse signals from the converter having a duty cycle having a longer low logic level interval than high logic level interval, a CMOS latch for receiving and latching the second output signals from the common gate amplifiers at logic levels compatible with circuits formed of CMOS elements, a CMOS double to single ended converter connected between a VDD voltage rail and VSS ground, for receiving the latched output signals, apparatus for providing an output signal referenced to VDD and ground from the converter.
REFERENCES:
patent: 5153465 (1992-10-01), Sandu
patent: 5317214 (1994-05-01), Lewis
patent: 5517148 (1996-05-01), Yin
patent: 5606268 (1997-02-01), Van Brunt
patent: 5614843 (1997-03-01), Mita et al.
Driscoll Benjamin D.
Pascal E. E.
PMC-Sierra Inc.
Westin Edward P.
Wilkes R. A.
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