CMOS semiconductor device with (LDD) NMOS and single drain PMOS

Details CMOS semiconductor device with (LDD) NMOS and single drain PMOS CMOS semiconductor device with (LDD) NMOS and single drain PMOS

1991-08-30

1994-03-01

Hille, Rolf

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257900, 257408, 257346, H01L 2994, H01L 31062, H01L 31113, H01L 27088

Patent

active

052910520

ABSTRACT:
A MOS semiconductor device and the methods for constructing the device. The MOS device provided with first and second MOS transistors are formed on two identical wafer sections. The impurity region of the first transistor and a first group of gate side wall spacers are aligned to the gate of the first transistor. The impurity region of the second transistor and a second group of gate side wall spacers are aligned to the gate of the second MOS transistor. The second group of gate side wall spacers have a thickness different from that of the first group of gate side wall spacers.

REFERENCES:
patent: 4577391 (1986-03-01), Hsia et al.
patent: 4661833 (1987-04-01), Mizutani
patent: 4937645 (1990-06-01), Ootsuka et al.
patent: 5021354 (1991-06-01), Pfiester
patent: 5023190 (1991-06-01), Lee et al.
patent: 5024960 (1991-06-01), Haken

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