CMOS semiconductor device containing N-channel transistor...

Details CMOS semiconductor device containing N-channel transistor... CMOS semiconductor device containing N-channel transistor...

1998-11-06

2001-06-12

Booth, Richard (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

Reexamination Certificate

active

06245623

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a method of manufacturing high density semiconductor devices having shallow lightly-doped junctions. The present invention has particular applicability in manufacturing high density semiconductor devices with design features of 0.25 microns and under.
BACKGROUND ART
The escalating requirements for high density and performance associated with ultra large scale integration semiconductor devices require design features of 0.25 microns and under, such as under 0.18 microns, increased transistor and circuit speeds, high reliability and increased manufacturing throughput. The reduction of design features to 0.25 microns and under challenges the limitations of conventional semiconductor methodology.
Conventional semiconductor devices typically comprise a semiconductor substrate, normally doped monocrystalline silicon, and a plurality of interlayered dielectric and conductive layers formed thereon. In a conventional semiconductor device
100
illustrated in
FIG. 1
, p-type substrate
1
is provided with field oxide
2
for isolating an active region comprising N+source/drain regions
3
, and a gate electrode
4
, typically of doped polysilicon, above the semiconductor substrate with gate oxide
5
therebetween. Interlayer dielectric layer
6
, typically silicon dioxide, is then deposited thereover and openings formed by conventional photolithographic and etching techniques. The openings are filled with conductive material to establish electrical contact between subsequently deposited conductive layer
8
, typically aluminum or an aluminum-base alloy, and source/drain regions
3
through contacts
7
, and to transistor gate electrode
49
. Dielectric layer
9
, typically silicon dioxide, is deposited on conductive layer
8
, and another conductive layer
10
, typically aluminum or an aluminum-base alloy, formed on dielectric layer
9
and electrically connected to conductive layer
8
through vias
11
.
With continued reference to
FIG. 1
, conductive layer
10
is the uppermost conductive layer and, hence, constitutes the wire bonding layer. Dielectric layer
12
, also typically silicon dioxide, is deposited, and a protective dielectric scratch resistant topside layer
13
deposited thereon. Protective dielectric layer
13
typically comprises a nitride layer, such as silicon nitride (Si
3
N
4
). Alternatively, protective dielectric layer
13
may comprise a dual topcoat comprising a nitride layer on an oxide layer. The protective dielectric layer
13
provides scratch protection to the semiconductor device and protection against moisture and impurity contamination during subsequent processing. After deposition of protective dielectric layer
13
, conventional photolithographic etching techniques are employed to form an opening to expose wire bonding layer
10
for external connection by means of bonding pad
14
and electrically conductive wires
15
or an external connection electrode (not shown).
Although only two conductive layers
8
and
10
are depicted in
FIG. 1
for illustrative convenience, conventional semiconductor devices are not so limited and may comprise more than two conductive layers, depending on design requirements, e.g. five conductive metal layers. Also in the interest of illustrative convenience,
FIG. 1
does not illustrate any particular type of plug or barrier layer technology. However, such technology is conventional and, therefore, the details of such features are not set forth herein.
As device features continually shrink in size, it becomes necessary to decrease the depth of the source and drain regions in the semiconductor substrate, i.e., the junction depth. For example, in forming a polycrystalline silicon gate having a length of about 0.25 microns, the junction depth (X
j
) should be no greater than about 800 Å. This objective is extremely difficult to achieve, particularly when implanting impurities to form N-type source/drain regions.
For example, in accordance with conventional methodology for forming N-channel transistors illustrated in
FIG. 2
, an N-type impurity such as arsenic is ion implanted, indicated by arrows
20
, into semiconductor substrate
1
at a minimal implantation energy, e.g., about 10-20 KeV, selected to achieve a shallow X
j
. Such implanted impurities form the lightly-doped drain (LDD) regions
22
upon subsequent activation annealing.
After such lightly-doped implants, a dielectric layer such as silicon oxide or silicon nitride, is deposited and etched to form insulating sidewall spacers
24
on the side surfaces of gate electrode
4
. In forming sidewall spacers
24
, gate oxide layer
5
is etched, thereby exposing the surface of semiconductor substrate
1
adjacent sidewall spacers
24
, as shown in FIG.
2
.
Adverting to
FIG. 3
, a thin screen oxide layer
30
is then thermally grown on the exposed surface of semiconductor substrate
1
and gate electrode
4
to reduce damage to substrate
1
during subsequent impurity implantation. N-type impurities, such as arsenic, are then ion implanted, as indicated by arrows
32
in
FIG. 3
, into substrate
1
to form the moderately-doped source/drain (MDD) or heavily-doped source/drain (HDD) implant regions
34
. Activation annealing is then conducted to activate LDD regions
22
and MDD/HDD regions
34
. Annealing is typically performed at a temperature of about 900° C. to about 1100° C. to activate the impurity implanted regions, thereby forming the source/drain regions of the N-channel transistor.
It has been found, however, that during annealing to activate the implanted dopants, arsenic diffuses into the crystalline semiconductor substrate
1
such that the junction depth exceeds the targeted maximum depth of about 800 Å. The causes of undefined dopant X
j
is believed to stem from various factors.
One cause for the increased X
j
is that arsenic, as well as other impurities typically used as dopants, exhibit oxidation-enhanced diffusion. That is, during processing steps employing oxidation, the diffusion of arsenic into the semiconductor substrate is enhanced, thereby significantly increasing X
j
. For example, growing thermal oxide screen layer
30
after the LDD implant regions are formed, results in an increased X
j
.
Additionally, growing thermal oxide screen layer
30
at a high temperature induces crystalline defects in substrate
1
. The implanted arsenic diffuse via the crystalline defects, such as interstitials. Accordingly, the diffusion of the arsenic, as measured by the junction depth, substantially increases X
j
beyond the targeted maximum as a result of the thermal oxidation processes used in conventional semiconductor processing.
The subsequent high temperature dopant activation anneal, also adds to the increased X
j
by inducing additional crystalline defects in the underlying semiconductor substrate. The implanted arsenic diffuses further via the crystalline defects, such that the junction depth of the arsenic greatly exceeds the targeted maximum depth of about 800 Å. Consequently the resulting dopant profile of arsenic, after the activation anneal, extends to about 1000 Å or more, which is considerably beyond the targeted maximum of about 800 Å. An undesirably deep X
j
causes the short channel effect, generating a leakage current, which degrades the performance of the semiconductor device.
Accordingly, there exists a need for a semiconductor device and a method of manufacturing a semiconductor device having shallow junction depths.
SUMMARY OF THE INVENTION
An object of the present invention is a method of manufacturing a semiconductor device having shallow junction depths.
Another object of the present invention is a semiconductor device having shallow junction depths.
Additional objects, advantages and other features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice

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