CMOS semiconductor device comprising graded N-LDD junctions with

Details CMOS semiconductor device comprising graded N-LDD junctions with CMOS semiconductor device comprising graded N-LDD junctions with

1997-09-05

2000-10-24

Whitehead, Jr., Carl

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257344, H01L 2976

Patent

active

061371378

ABSTRACT:
A CMOS semiconductor device is formed having an N-channel transistor comprising a source/drain region and an N-LDD region with a graded junction. The graded N-LDD junction is obtained by implanting a high diffusivity N-type impurity, such as P, after the N-LDD implant, e.g., As, subsequent to sidewall spacer formation. Upon activation annealing to form the N-channel transistor source/drain regions, P diffuses to a greater depth than As, thereby forming a deeper and graded N-LDD junction.

REFERENCES:
patent: 5422506 (1995-06-01), Zamapian
patent: 5565700 (1996-10-01), Chou et al.
D. Nayak, et al., in "A Comprehensive Study of Performance and Reliability of P, As, and Hybrid As/p N-LDD Junctions for Deep-Submicron CMOS Logic Technology," IEEE Electron Device Letters, vol. 18, No. 6, 1997, pp. 281-283.

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