CMOS semiconductor device comprising graded junctions with reduc

Details CMOS semiconductor device comprising graded junctions with reduc CMOS semiconductor device comprising graded junctions with reduc

1999-06-04

2000-08-22

Hardy, David

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438303, 438305, 438299, 438199, 257344, 257336, H01L 21336

Patent

active

061071498

ABSTRACT:
A CMOS semiconductor device is formed having an N-channel transistor comprising a graded junction with reduced junction capacitance. The graded junction is achieved by forming a second sidewall spacer on the gate electrode, after source/drain implantations, and ion-implanting an N-type impurity with high diffusivity, e.g., P into an A.sub.5 implant, followed by activation annealing.

REFERENCES:
patent: 5583067 (1996-12-01), Sanchez
patent: 5943565 (1999-08-01), Ju

Affiliated with

Also associated with

Rating

CMOS semiconductor device comprising graded junctions with reduc does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with CMOS semiconductor device comprising graded junctions with reduc, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and CMOS semiconductor device comprising graded junctions with reduc will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-580316