CMOS pull-up input network

Details CMOS pull-up input network CMOS pull-up input network

1993-05-26

1995-08-08

Hudspeth, David R.

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Signal level or switching threshold stabilization

326 31, 326 83, H03K 1716

Patent

active

054402425

ABSTRACT:
A CMOS logic circuit with biased inputs to a predetermined logic level, being of a type including at least one signal input terminal and logic gates for acting on an input signal, and further including a circuit portion which is connected to the signal input terminal, and includes a high-value resistance effective to bias the input signal.

REFERENCES:
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patent: 4472647 (1984-09-01), Allgood et al.
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patent: 5227677 (1993-07-01), Furman
patent: 5264744 (1993-11-01), Mizukami et al.
patent: 5287022 (1994-02-01), Wilsher
Patent Abstracts of Japan, vol. 8, No. 167, (E-358) (1604) Aug. 2, 1984, & JP-A-59064916 (Toshiba KK) Apr. 13, 1984.
Patent Abstracts of Japan, vol. 13, No. 507 (E-845) (3855) Nov. 14, 1989 & JP-A-1204520 (Mitsubishi Electric Corp.) Aug. 17, 1989.

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