Cmos processs with low thermal budget

Details Cmos processs with low thermal budget Cmos processs with low thermal budget

1999-05-03

2001-10-02

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S299000, C438S303000, C438S595000

Reexamination Certificate

active

06297115

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to integrated circuits and to methods of manufacturing integrated circuits. More particularly, the present invention relates to a method of manufacturing integrated circuits in a low thermal budget process.
BACKGROUND OF THE INVENTION
Integrated circuits (ICs), such as, ultra-large scale integrated (ULSI) circuits, can include as many as one million transistors or more. The ULSI circuit often includes complementary metal oxide semiconductor (CMOS) field effect transistors (FET).
Conventional transistors are generally comprised of gates disposed between drain and source regions. The drain and source regions are typically located within a semiconductor film or substrate, and the gates are provided on a top surface of film or substrate. The drain and source regions can be heavily doped with a P-type dopant (e.g., boron) or an N-type dopant (e.g., phosphorous).
The drain and source regions generally include a thin extension that is disposed partially underneath the gate to enhance the transistor performance. Shallow source and drain extensions help to achieve immunity to short-channel effects which degrade transistor performance for both N-channel and P-channel transistors. Short-channel effects can cause threshold voltage roll-off and drain-induced barrier-lowering. Shallow source and drain extensions and, hence, controlling short-channel effects, are particularly important as transistors become smaller.
Conventional techniques utilize a double implant process to form shallow source and drain extensions. According to the conventional process, the source and drain extensions are formed by providing a transistor gate structure without sidewall spacers on a top surface of a silicon substrate. The silicon substrate is doped on both sides of the gate structure via a conventional doping process, such as, a diffusion process or ion implantation process. Without the sidewall spacers, the doping process introduces dopants into a shallow or thin region (i.e., just below the top surface of the substrate) to form the drain and source extensions, as well as to partially form the drain and source regions.
After the drain and source extensions are formed, silicon dioxide spacers, which abut lateral sides of the gate structure, are provided over the source and drain extensions. The substrate is doped a second time to form the deeper source and drain regions. The source and drain extensions are not further doped due to the blocking capability of the silicon dioxide spacer.
As transistors disposed on integrated circuits (ICs) become smaller, transistors with shallow and ultra-shallow source/drain extensions have become more difficult to manufacture. For example, smaller transistors should have ultra-shallow source and drain extensions (less than 30 or 40 nanometer (nm) junction depth). Forming source and drain extensions with junction depths of less than 30 nm is very difficult using conventional fabrication techniques. Conventional ion implantation and diffusion doping techniques make transistors on the IC susceptible to short-channeling effects, which result in a dopant profile tail distribution that extends deep into the substrate. Also, conventional ion implantation techniques have difficulty maintaining shallow source and drain extensions because point defects generated in bulk semiconductor substrate during ion implantation can cause the dopant to diffuse more easily (transient enhanced diffusion, TED). The diffusion often extends the source and drain extension vertically into the bulk semiconductor substrate.
Heretofore, CMOS processes have required furnace anneal processes, rapid thermal anneal (RTA) processes, and spike RTA processes to temporarily heat the substrate. The heating processes are required to diffuse and to activate dopants in polysilicon gate materials, in the source region, and in the drain region. Additionally, heating processes are also utilized during the deposition of certain materials, the silicidation of metals, and other fabrication steps. The heating processes significantly increase the thermal budget of the CMOS process. For example, even spike RTA processes subject the substrate to at least one second of high temperature treatment (e.g., over 900° C.).
The total thermal budget dopants experienced by the IC becomes more critical as transistors become smaller. For example, dopants in the source region, drain region, and gate region diffuse more readily in response to high temperatures. Accordingly, high temperatures can adversely affect ultra-shallow junction formation, the formation of ultra-tight dopant profiles for halo implants and retrograde channel implants, and dopant penetration into the gate (boron penetration into the gate of a P-channel transistor). Ultra-shallow junctions and tight profile pocket regions improve immunity to short-channel effects, such as, threshold voltage roll-off. Short-channel effects are a major barrier to appropriate transistor scaling.
Thus, there is a need for a method of manufacturing a transistor that does not utilize a conventional annealing process step. Further still, there is a need for transistors that can be manufactured within a low thermal budget. Even further still, there is a need for an efficient method of manufacturing source and drain extensions that minimizes ion implantation channeling effect.
SUMMARY OF THE INVENTION
The present invention relates to a method of manufacturing an integrated circuit. The method includes forming at least a portion of a gate structure on a top surface of a silicon substrate, providing a first amorphization implant. The gate structure includes an amorphous layer, and the amorphization implant creates a first amorphous region near the top surface of the substrate. The method further includes providing spacers which abut the gate structure, providing a second amorphization implant, doping the substrate in the amorphous layer, and thermally annealing the substrate. The second amorphization implant creates a deep amorphous region in the substrate.
The present invention further relates to a method of manufacturing an ultra-large scale integrated circuit including a plurality of field effect transistors. The method includes steps of forming at least part of a gate structure on a top surface of a semiconductor substrate, providing a shallow amorphization implant, providing spacers, providing a deep amorphization implant, doping the substrate to form source and drain regions, and thermally annealing the substrate in a low thermal budget process. The shallow amorphization implant creates a shallow amorphous region near the top surface, and the deep amorphization implant creates a deep amorphous region in the substrate. The spacers abut the gate structure.
The present invention even further still relates to a method of fabricating field effect transistors associated with an ultra-large scale integrated circuit. The method includes forming a plurality of at least a portion of gate structures on a top surface of a silicon substrate, providing a first amorphization implant, providing spacers, providing a second amorphization implant, doping the substrate, providing a dielectric layer over the gate structure and the substrate, providing a metal layer over the dielectric layer, and annealing the substrate. The first amorphization implant creates a first amorphous region near the top surface of the substrate. The second amorphization implant creates a deep amorphous semiconductor region in the substrate.


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