Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-11-06
2001-05-15
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S301000, C438S527000
Reexamination Certificate
active
06232166
ABSTRACT:
CROSS REFERENCE TO THE RELATED APPLICATIONS
The subject matter involved in this application is related to the subject matter involved in commonly-assigned, co-pending application Ser. No. 08/924,640, filed Sep. 5, 1997, now U.S. Pat. No. 5,943,565 issued on Aug. 24, 1999, entitled CMOS PROCESSING EMPLOYING SEPARATE SPACERS FOR INDEPENDENTLY OPTIMIZED TRANSISTOR PERFORMANCE.
1. Technical Field
The present invention relates to a method of manufacturing a semiconductor device with improved reliability and increased manufacturing throughput. The invention has particular applicability in manufacturing high density CMOS semiconductor devices with design features of 0.25 microns and under.
2. Background Art
The escalating requirements for high density and performance associated with ultra large scale integration semiconductor devices require design features of 0.25 microns and under, such as 0.18 microns and under, increased transistor and circuit speeds, high reliability and increased manufacturing throughput. The reduction of design features to 0.25 microns and under challenges the limitations of conventional semiconductor manufacturing techniques.
As design features continually shrink in size, the likelihood of short-channel effects increases. For example, subsurface punchthrough occurs when the source and drain depletion regions are formed too close to each other, resulting in the generation of a leakage current which adversely affects circuit performance.
A conventional method of preventing subsurface punchthrough in MOSFETs involves the formation of halo implants, as illustrated in FIG.
1
. Adverting to
FIG. 1
, an initial gate dielectric layer
12
, such as silicon oxide, is formed on semiconductor substrate
10
and a gate electrode layer formed thereon, as in conventional practices. The gate electrode layer is etched in a conventional manner to form gate electrode
14
on the underlying gate oxide layer
12
.
Using gate electrode
14
as a mask, a P-type impurity, such as boron, is implanted as indicated by arrows
16
to form source/drain implants
18
. Subsequent to the formation of source/drain implants
18
, an N-type impurity is implanted to form halo implant regions
19
, to avoid short-channel effects characteristic of P-type transistors.
A drawback attendant upon the formation of halo implant regions
19
is that a large-angle tilt implant is required to implant the N-type impurity to the required lateral penetration and depth. Typically, an N-type impurity such as phosphorous is implanted at an angle greater than 30°, as indicated by arrows
20
. The large-angle tilt implant is typically performed twice to complete halo implant regions
19
, requiring rotation of semiconductor
10
between segments. In certain semiconductor structures in which gates are oriented at right angles to other gates, four separate large-angle tilt implants are required to form the halo implant regions, requiring four rotations of semiconductor
10
. Such processing is time consuming, thereby significantly reducing manufacturing throughput and increasing production costs.
Accordingly, there exists a need for methodology in forming semiconductor devices with significantly reduced susceptibility to short-channel effects while maintaining high manufacturing throughput.
SUMMARY OF THE INVENTION
An object of the present invention is a method of manufacturing a semiconductor device with halo implants in an efficient, cost-effective manner.
Additional objects, advantages and other features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the invention. The objects and advantages of the invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other objects are achieved in part by a method of manufacturing a P-channel CMOS semiconductor device. The method includes forming a dielectric layer on a surface of a semiconductor substrate and forming a conductive layer on the dielectric layer. The method also includes patterning the conductive layer to form a gate electrode having an upper surface and side surfaces. The method further includes implanting N-type impurities at a zero degree tilt angle to form halo implant regions in the semiconductor substrate.
Another aspect of the invention is a method of manufacturing a CMOS semiconductor device comprising an N-channel transistor and P-channel transistor. The method includes forming a dielectric layer on a surface of a semiconductor substrate and forming a conductive layer on the dielectric layer. The method also includes patterning the conductive layer to form a first gate electrode of the N-channel transistor and a second gate electrode of the P-channel transistor, each gate electrode having an upper surface and side surfaces. The method further includes using the first gate electrode as a mask and implanting N-type impurities to form N-type lightly doped implant regions of the N-channel transistor in the semiconductor substrate. The method also includes using the second gate electrode as a mask and implanting N-type impurities at a zero degree tilt angle to form halo implant regions of the P-channel transistor in the semiconductor substrate.
Other objects and advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description. The embodiments shown and described provide illustration of the best mode contemplated for carrying out the invention. The invention is capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
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Ju Dong-Hyuk
Luning Scott
Advanced Micro Devices , Inc.
Lattin Christopher
Niebling John F.
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