CMOS processing employing separate spacers for independently opt

Details CMOS processing employing separate spacers for independently opt CMOS processing employing separate spacers for independently opt

1997-09-05

1999-08-24

Trinh, Michael

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438232, H01L 218238

Patent

active

059435658

ABSTRACT:
N-channel and P-channel transistor performances are separately optimized by activating the source/drain regions of the N-channel transistor before forming the P-channel lightly doped implant. Separate sidewall spacers for the moderately or heavily doped implants of the N- and P-channel transistors are employed. Embodiments enable independent control of the junction depths and channel lengths of N- and P-channel transistors.

REFERENCES:
patent: 4637124 (1987-01-01), Okuyama et al.
patent: 4891326 (1990-01-01), Koyanagi
patent: 5169796 (1992-12-01), Murray et al.
patent: 5278441 (1994-01-01), Kang et al.
patent: 5438008 (1995-08-01), Ema
patent: 5610088 (1997-03-01), Chang et al.
patent: 5654212 (1997-08-01), Jang
patent: 5714413 (1998-02-01), Brigham et al.
patent: 5747373 (1998-05-01), Yu
patent: 5786247 (1998-07-01), Chang et al.

Affiliated with

Also associated with

Rating

CMOS processing employing separate spacers for independently opt does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with CMOS processing employing separate spacers for independently opt, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and CMOS processing employing separate spacers for independently opt will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-476081