CMOS process with optimized PMOS and NMOS transistor devices

Details CMOS process with optimized PMOS and NMOS transistor devices CMOS process with optimized PMOS and NMOS transistor devices

2011-08-23

2011-08-23

Nguyen, Ha Tran T (Department: 2829)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

Reexamination Certificate

active

08003454

ABSTRACT:
A semiconductor process and apparatus includes forming NMOS and PMOS transistors (24, 34) with enhanced hole mobility in the channel region of a transistor by selectively relaxing part of a biaxial-tensile strained semiconductor layer (90) in a PMOS device area (97) to form a relaxed semiconductor layer (91), and then epitaxially growing a bi-axially stressed silicon germanium channel region layer (22) prior to forming the NMOS and PMOS gate structures (26, 36) overlying the channel regions, and then depositing a contact etch stop layer (53-56) over the NMOS and PMOS gate structures. Embedded silicon germanium source/drain regions (84) may also be formed adjacent to the PMOS gate structure (70) to provide an additional uni-axial stress to the bi-axially stressed channel region.

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