CMOS process for forming planarized twin wells

Details CMOS process for forming planarized twin wells CMOS process for forming planarized twin wells

1999-04-15

2001-04-03

Dang, Trung (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S221000, C438S224000, C438S296000, C438S424000

Reexamination Certificate

active

06211002

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method for forming twin-wells for a complementary mental oxide semiconductor (CMOS) device, and particularly to a process for forming planarized twin-wells structure.
BACKGROUND OF THE INVENTION
The metal oxide semiconductor (MOS) transistor, including N-channel MOS (NMOS), P-channel MOS (PMOS) and complementary MOS (CMOS), is one of the most important devices in integrated circuit technology today. And, because of the high loss of energy and the high generation of heat, the stability and the reliability of NMOS and PMOS are poor. They are gradually replaced by CMOS when the integration of the semiconductor device becomes higher and higher.
There are three types of CMOS devices: P-well type, N-well type and twin-wells type. The CMOS devices of P-well type are fabricated by forming N-channel devices in P-wells, while the P-channel devices are formed in the N-type substrate outside the P-wells. Contrarily, the CMOS devices of N-well type are fabricated by forming P-channel devices in N-wells, while the N-channel devices are formed in the P-type substrate outside the N-wells. The devices with twin-wells structure are fabricated with both types of wells built in either type substrate independently, while there is one MOS devices of opposite type formed in each well respectively.
The selection of the well types described above depends mostly on the circuit application. For example, the N-well technique is often used for fabricating dynamic random access memories (DRAMs) because P-channel devices have low substrate current whereas the high substrate current can be easily sunk from the P-type substrate. And the P-well technique has a benefit in its simpler fabrication because the P-well devices are less sensitive to field inversion and then the P-well itself can be used to be the channel stop for N-channel. The twin-wells structure, wherein the doping profiles in each well could be set independently to optimize both device types, is suitable to be used in the high integration circuit of sub-micron devices. In addition, the twin-wells structure has lower junction capacitance and lower body effect, and it has the flexibility of selecting substrate type without affecting performance. These advantages make the twin-wells a better structure than the N-well and the P-well structure.
Recently, there are three methods provided for fabricating the twin-wells structure These are disclosed in the following references Ruojia Lee, et al. in U. S. Pat. No. 5,024,961 titled “Blanket Punchthrough and Field-isolation Implant for Sub-micron N-channel CMOS Devices”, Douglas C. H. Yu, et al. in “Low Threshold Voltage CMOS Devices with Smooth Topography for 1 Volt Application” IEDM Tech. Dig., Vol. 94, p. 489, (1994); and C. T. Liu, et al. in “0.2-&mgr;m n-Channel and p-Channel MOSFET's Integrated on Oxidation-Planarized Twin-Tubs” IEEE Electron Device Letter, Vol. 17, p. 500 (1996). But all of these three methods will also have poor topographies, that is, a nonplanar surface occurs at or near the interface of the P and the N-well due to the high temperature oxidation used over one well. Although a height difference is useful for subsequent lithography for fabricating these devices, a large difference makes the transitional area between the P-well and N-well wasteful. Therefore, there is a need for a simplified and an improved method for fabricating CMOS devices with twin-wells structure.
SUMMARY OF THE INVENTION
A process for forming twin-wells devices with smooth surface topography is disclosed. After depositing pad oxide and a silicon nitride layers, a photoresist is patterned on the silicon nitride layers to define the N-well region. Next, a high-energy phosphorus ion implantation is performed to form the N-well by using the patterned photoresist as a mask. A thick oxide layer deposited by liquid phase deposition process is then grown on the N-well region part of the silicon nitride layer, but not on the photoresist. After stripping the photoresist, a high-energy boron ion implantation is carried out to form the P-well by using the LPD-oxide layer as a mask. The thick LPD-oxide layer is removed by BOE or HF solution. Trenched isolation regions are formed to isolate and define active regions. The dopants are activated and driven in to form twin-wells at this step. After removing the pad oxide and the silicon nitride layer, the CMOS device is fabricated by standard processes.


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