Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-03-29
2003-12-30
Nhu, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S137000, C438S212000
Reexamination Certificate
active
06670230
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to a CMOS (Complementary Metal Oxide Semiconductor) process. In particular, the present invention relates to a CMOS process for double vertical channel thin film transistor (DVC TFT).
2. Description of the Related Art
Conventionally, CMOS circuits are fabricated in crystalline Si substrates to take the advantage of high carrier mobility. However, the circuit speed is often limited by the relatively low effective mobility in a polysilicon MOSFET channel resulting from grain boundary carrier scattering. Even when using hydrogen passivation process as to minimize scattering, the OFF currents are still too high for most applications or the devices degrade after long-term bias stressing.
The most commonly used method to increase the current drive is to increase the channel width. However, leakage current increases with channel width, resulting in a trade off in desired performance. On the other hand, the conventional CMOS process is very complicated and expensive, thereby reducing the steps of the CMOS process is very important.
SUMMARY OF THE INVENTION
The present invention is intended to overcome the above-described disadvantages.
Therefore, the first object of the present invention is to provide a CMOS process for double vertical channel thin film transistor, including the steps of: forming a gate layer on a substrate; forming a first insulator layer on the substrate and the gate layer; forming a semiconductor layer on the first insulator layer, wherein the semiconductor layer has a first area, a second area, and a third area, the third area being formed between the first area and the second area; forming a first mask on the first area, and implanting N
+
ions to the second area to define a first doped area and a second channel area, and removing the first mask; forming a second mask on the second area, and implanting P
+
ions to the first area to define a second doped area, a first channel area, and an intrinsic area between the first area and second area, and removing the second mask; forming a second insulator layer on the first doped area, the second doped area, the first channel area, the second channel area, and the intrinsic area between the first area and second area; exposing the first doped area and the second doped area at the edges of the first insulator layer; and
forming a metal layer on the exposed first doped area and the exposed second doped area.
The second object of the present invention is to provide a CMOS process for double vertical channel thin film transistor, including the steps of: forming a gate layer on a substrate; forming a first insulator layer on the substrate and the gate layer; forming a semiconductor layer on the first insulator layer, wherein the semiconductor layer has a first area, a second area, and a third area, the third area being formed between the first area and the second area; forming a first mask on the first area, and implanting N
+
ions to the second area to define a first doped area and a second channel area, and removing the first mask; forming a second mask on the second area, and implanting P
+
ions to the first area to define a second doped area, a first channel area, and an intrinsic area between the first area and second area, and removing the second mask; forming a second insulator layer covering over the first channel area and the second channel area; and forming a metal layer on the first doped area, the second doped area, and the intrinsic area.
The third object of the present invention is to provide a CMOS of double vertical channel thin film transistor, including: a gate layer formed on a substrate; a first insulator layer formed on the substrate and the gate layer, wherein the first insulator layer has a flat part and two vertical walls, the flat part being formed between the two vertical walls; a semiconductor layer formed on the first insulator layer, wherein the semiconductor layer has two channels formed on the two vertical walls, and a first doped area and a second doped area formed to connect with the ends of the two channels respectively, and an intrinsic area formed on the flat part between the first doped area and the second doped area; a second insulator layer formed on the semiconductor layer, exposing the sides of the semiconductor layer to form an exposed pattern of the semiconductor layer; and a metal layer formed on the exposed pattern of the semiconductor layer.
The forth object of the present invention is to provide a CMOS of double vertical channel thin film transistor, including: a gate layer formed on a substrate; a first insulator layer formed on the substrate and the gate layer, wherein the first insulator layer has a flat part and two vertical walls, the flat part being formed between the two vertical walls; a semiconductor layer formed on the first insulator layer, wherein the semiconductor layer has two channels formed on the two vertical walls, and a first doped area and a second doped area formed to connect with the ends of the two channels respectively, and an intrinsic area formed on the flat part between the first doped area and the second doped area; a second insulator layer formed and covering over the two channels; and a metal layer formed on the semiconductor layer separately.
The process of the present invention successfully decreases the fabrication cost by simplifying the conventional CMOS process. Furthermore, leakage current is also reduced in the above CMOS with a dual gate and offset structure. Moreover, the double vertical channel (DVC) structure of the above CMOS side steps the photolithography limitation because the deep-submicrometer channel length is determined by the thickness of gate, thereby decreasing the channel length substantially.
REFERENCES:
patent: 5747856 (1998-05-01), Chen et al.
patent: 6407431 (2002-06-01), Yamazaki et al.
patent: 6458633 (2002-10-01), Cho
Hannstar Display Corp.
Merchant & Gould P.C.
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