CMOS precharge and equalization circuit

Details CMOS precharge and equalization circuit CMOS precharge and equalization circuit

1990-02-15

1991-07-30

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Precharge

365202, G11C 700

Patent

active

050364928

ABSTRACT:
A CMOS precharge and equalization circuit for use with memory cells coupled between paired bit lines in a static random access memory array is constructed without the use of bleeder circuits. The precharge and equalization circuit is formed of a pair of precharge transistors and a pair of equalization transistors for precharging and equalizing the paired bit lines.

REFERENCES:
patent: 4712193 (1987-12-01), Sood
patent: 4780852 (1988-10-01), Kajigaya et al.
patent: 4893278 (1990-01-01), Ito
Gladstein, A. et al., "Elimination of Bitline Charging through a Thick Oxide FET Read-Only Storage Device", IBM Technical Disclosure Bulletin, vol. 21, No. 6, November 1978, pp. 2593-2594.

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