CMOS performance enhancement using localized voids and...

Details CMOS performance enhancement using localized voids and... CMOS performance enhancement using localized voids and...

2005-02-22

2005-02-22

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S199000

Reexamination Certificate

active

06858488

ABSTRACT:
The speed of CMOS circuits is improved by imposing a longitudinal tensile stress on the NFETs and a longitudinal compressive stress on the PFETs, by implanting in the sources and drains if the NFETs ions from the eighth column of the periodic table and hydrogen and implanting in the sources and drains of the PFETs ions from the fourth and sixth columns of the periodic table.

REFERENCES:
patent: 6057581 (2000-05-01), Doan
patent: 6075262 (2000-06-01), Moriuchi et al.
patent: 6258695 (2001-07-01), Dunn et al.
patent: 6429084 (2002-08-01), Park et al.
IEDM 2000 “Mechanical stress effect of etch-stop nitride and its impact on deep submicron transistor design”, Ito et al., NEC Corporation, ppgs 10.7.01-10.7.4.

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