CMOS output buffer circuit exhibiting reduced switching noise

Details CMOS output buffer circuit exhibiting reduced switching noise CMOS output buffer circuit exhibiting reduced switching noise

1997-04-03

1999-07-13

Santamauro, Jon

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Output switching noise reduction

326 58, 326 86, 326 87, H03K 1716, H03K 190185

Patent

active

059231831

ABSTRACT:
A CMOS output buffer circuit includes a predriving circuit which generates two predriving signals, a main driving circuit which has a plurality of parallel connected pull-up transistors and a plurality of parallel connected pull-down transistors, and a sequential driving circuit which provides sequential pull-up and pull-down driving signals to the pull-up and pull-down transistors, respectively. The main driving circuit generates the output signal according to the sequential pull-up or pull-down driving signals, whereby the output signal is developed step by step into either the power supply potential or the ground potential. In the manner, any spike in the switching current is considerably mitigated, thereby reducing switching noise.

REFERENCES:
patent: 4719369 (1988-01-01), Ason et al.
patent: 5122690 (1992-06-01), Bianchi
patent: 5166555 (1992-11-01), Kano
patent: 5534791 (1996-07-01), Mattos et al.
patent: 5537060 (1996-07-01), Baek

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