CMOS manufacturing process with self-amorphized source/drain...

Details CMOS manufacturing process with self-amorphized source/drain... CMOS manufacturing process with self-amorphized source/drain...

2000-07-18

2003-10-07

Trinh, Michael (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S301000, C438S303000

Reexamination Certificate

active

06630386

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to the field of integrated circuits and to methods of manufacturing integrated circuits. More particularly, the present invention relates to a low thermal budget method of manufacturing an integrated circuit with self-amorphized source/drain junctions and extensions.
BACKGROUND OF THE INVENTION
Integrated circuits (ICs), such as, ultra-large scale integrated (ULSI) circuits, can include as many as one million transistors or more. The ULSI circuit can include complementary metal oxide semiconductor (CMOS) field effect transistors (FETs) or MOSFETs. The transistors can include semiconductor gates disposed between drain and source regions. The drain and source regions are typically heavily doped with a P-type dopant (boron) or an N-type dopant (phosphorous).
The drain and source regions generally include a thin extension that is disposed partially underneath the gate to enhance the transistor performance. Shallow source and drain extensions help to achieve immunity to short-channel effects which degrade transistor performance for both N-channel and P-channel transistors. Short-channel effects can cause threshold voltage roll-off and drain-induced barrier-lowering. Thus, controlling short channel effects is important to assuring proper semiconductor operation.
Conventional techniques utilize a double implant process to form shallow source and drain extensions. According to the conventional process, the source and drain extensions are formed by providing a transistor gate structure without sidewall spacers on a top surface of a silicon substrate. The silicon substrate is doped on both sides of the gate structure via a conventional doping process, such as, a diffusion process or ion implantation process. Without the sidewall spacers, the doping process introduces dopants into a thin region (i.e., just below the top surface of the substrate) to form the drain and source extensions as well as to partially form the drain and source regions.
After the drain and source extensions are formed, silicon dioxide spacers, which abut lateral sides of the gate structure, are provided over the source and drain extensions. The substrate is doped a second time to form the deeper source and drain regions. The source and drain extensions are not further doped due to the blocking capability of the silicon dioxide spacers.
As the critical dimensions of transistors continue to shrink, control of thermal budget in IC fabrication is very important. The formation of ultra-shallow source/drain extensions and a super localized halo profile is critical to control short-channel effects. In conventional CMOS processes, high temperature (e.g., >1000° C.) rapid thermal annealing (RTA) is used to activate the dopant in the source, drain, halo, etc. With continually shrinking MOSFET dimensions, high-k materials (e.g., Al
2
O
3
, TiO
2
, ZrO
2
, etc.) may be used as gate insulators. Unfortunately, high-k materials tend to react with silicon at high temperatures. As such, the processing temperature has to be kept low (e.g., <800° C.) if high-k materials are to be used as gate dielectrics.
Thus, there is a need for a manufacturing process for CMOS integrated circuits in which post-gate processing temperatures are lower such that high-k materials used as gate insulators do not react with silicon. Further, there is a need for a transistor fabrication process which uses a differential anneal strategy. Even further, there is a need for using a heavy dose dopant implant for the shallow source/drain extension and deep source/drain contact junctions such that self-amorphization is possible. Even further still, there is a need for an IC manufacturing process in which a steep source/drain junction is obtained.
SUMMARY OF THE INVENTION
One aspect of one embodiment relates to a method of manufacturing an integrated circuit. The method includes annealing a gate structure and a halo section disposed over a substrate using a first temperature, implanting dopants to form drain and source regions, and annealing drain and source regions at a second temperature. The second temperature is substantially less than the first temperature.
Briefly, another aspect of an exemplary embodiment is related to a process of forming source and drain regions in an integrated circuit. The process includes providing a heavy-dose shallow source and drain extension implant which forms a self-amorphized shallow source and drain extension, providing a heavy-dose deep source and drain implant which forms a self-amorphized deep source and drain, and recrystallizing the shallow source and drain extension and deep source and drain.
Briefly, another aspect of an exemplary embodiment is related to a method of manufacturing a transistor on an ultra-large scale integrated circuit. The transistor has active regions including a source and a drain and a gate insulator made of a high-k material. The method includes the steps of implanting a dopant into a substrate to form a source and drain, in which the dopant has a dosage which causes source and drain to be self-amorphized, and recrystallizing the self-amorphized source and drain by applying a furnace anneal.


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