CMOS integration process having vertical channel

Details CMOS integration process having vertical channel CMOS integration process having vertical channel

1996-06-17

1999-10-05

Niebling, John

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438213, 438270, 438277, 438279, 438283, 257334, H01L 218238

Patent

active

059638001

ABSTRACT:
The present invention relates to processes for fabrictation of Vertical MISFET devices or a stack of several Vertical MISFET devices having high fabrication yield.

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"Fabrication of Three-Terminal Resonant Tunneling Devices in Silicon-Based Material," Zaslavsky, et al., Appl. Phys. Lett. 64 (13), pp. 1699-1701, Mar. 28, 1994.
"Ballistic Metal-Oxide-Semiconductor Field Effect Transistor," Natori, K., J. Appl. Phys. 76 (8), pp. 4879-4890, Oct. 15, 1994.
"The Physics and Device Applications of Epitaxially Grown Si and Si.sub.1-x GE.sub.x Heterostructures," Kearney, M.J., GEC Journal of Research vol. 10, No. 3, pp. 158-165, 1993.

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