CMOS integrated circuit with reduced susceptibility to PMOS punc

Details CMOS integrated circuit with reduced susceptibility to PMOS punc CMOS integrated circuit with reduced susceptibility to PMOS punc

1992-06-16

1997-11-18

Wilczewski, Mary

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438228, 438231, H01L 21336, H01L 218238

Patent

active

056887221

ABSTRACT:
A CMOS integrated circuit, in which the PMOS devices each include a buried channel region (26). The P+ source/drain regions (54) and (56) are separated from the channel region (26) by N-type lateral field isolating regions (58) and (60). Whenever a voltage negative enough to turn on the channel is applied, the isolating regions will be inverted by the electric fields from the comers of the gate. Thus, the value of the transistor's threshold voltage is not changed. However, these lateral field isolating regions provide an electric field modification which helps to minimize drain-induced barrier lowering, and thereby reduces the leakage current of the device in the off state. Preferably the lateral field isolating regions are formed by a doping which is maximal at the same depth (below the gate oxide) at which the threshold-voltage-adjust doping of the channel is maximal.
The preferred CMOS process provides lateral field isolating regions on the PMOS devices, and also provides LDD regions on the NMOS devices. The lateral field isolating regions in the PMOS transistors are formed by a blanket N-type implant, and the LDD regions in the NMOS transistors are formed by a patterned implant. Both of these implanting steps are preferably performed after the polysilicon gate layer is encapsulated (by a thin oxide layer), but before the sidewall oxide spacers (which will define a lateral separation between the fate level and the source/drain implant locations) are formed.

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