CMOS integrated circuit formed by using removable spacers to pro

Details CMOS integrated circuit formed by using removable spacers to pro CMOS integrated circuit formed by using removable spacers to pro

1997-01-10

1998-11-17

Wojciechowicz, Edward

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438251, 438275, 438286, 438308, 438519, 438522, 438530, 257336, 257344, 257369, 257372, 257408, H01L 2182

Patent

active

058375724

ABSTRACT:
An integrated circuit is provided having both NMOS transistors and PMOS transistors. The NMOS transistor junction regions are preferably formed before the PMOS transistor junction regions with pre-defined anneal temperatures applied after select implant steps. Both the NMOS and PMOS transistor junction are graded such that the drain areas include a relatively large LDD implant area and the source junctions do not. Whatever LDD area pre-existing in the source implanted with a higher concentration source/drain or MDD implant. The ensuing integrated circuit is therefore a CMOS circuit having asymmetrical transistor junctions and carefully controlled implant and anneal sequences. The asymmetrical junctions are retained, or at least optimized, by controlling the anneal temperatures such that diffusivity distances of n-type implants are relatively similar to p-type implants. Diffusivity is controlled by regulating the post-implant anneal temperatures of p-type implants lesser than previous n-type implants.

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