CMOS integrated circuit and method for implanting NMOS...

Details CMOS integrated circuit and method for implanting NMOS... CMOS integrated circuit and method for implanting NMOS...

1998-09-08

2001-07-10

Fabarry, Wael (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S230000, C438S232000, C438S217000, C257S336000, C257S344000

Reexamination Certificate

active

06258646

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor processing and, more particularly, to a method of forming a lightly doped drain structure in which implants associated with an n-channel transistor implants are formed prior to implants associated with a p-channel transistor.
2. Description of Relevant Art
Fabrication of a metal-oxide-semiconductor (“MOS”) transistor is well-known. Fabrication begins by lightly doping a single crystal silicon substrate as either n-type or p-type. The specific area where the transistor will be formed is then isolated from other areas on the substrate with the use of isolation structures. In modern fabrication technologies, the isolation structures may comprise shallow trenches in the substrate filled with dielectric oxide which acts as an insulator. Isolation structures may alternatively comprise, for example, locally oxidized silicon (“LOCOS”) structures well known in the art. A gate dielectric may be formed by oxidizing the silicon substrate. Oxidation is generally performed in a thermal oxidation furnace or, alternatively, in a rapid thermal anneal (“RTA”) apparatus. A gate conductor is then patterned from a layer of polycrystalline silicon (“polysilicon”) deposited on the gate dielectric. The polysilicon is rendered conductive by doping it with ions from an implanter or a diffusion furnace. The gate conductor is patterned using a mask followed by exposure, development, and etching. Subsequently, source and drain regions are doped, via ion implantation, with a high dosage n-type or p-type dopant. If the source and drain regions are doped n-type, the transistor is referred to as NMOS, and if the source and drain regions are doped p-type, the transistor is referred to as PMOS. A channel region between the source and the drain is protected from the implant species by the pre-existing gate conductor. When voltage above a certain threshold is applied to the gate of an enhancement-mode transistor, the channel between the source and drain becomes conductive and the transistor turns on.
NMOS remained the dominant MOS technology as long as the integration level of devices on a chip was sufficiently low. It is somewhat inexpensive to fabricate, NMOS integrated circuits which are functionally dense, and faster than PMOS integrated circuits. NMOS logic gates (i.e., inverters) draw DC power during one of the inverter states. Therefore, an NMOS integrated circuit will draw a steady current even when being operated in the standby mode (i.e., even when no signal is being propagated through the circuit). During the modem VLSI era, power consumption in NMOS circuits began to exceed tolerable limits. A lower power technology was needed to exploit the VLSI techniques. Complimentary MOS (“CMOS”) represented such a technology. CMOS integrated circuits use a combination of an NMOS transistor with a PMOS transistor. Therefore, in a CMOS inverter (unlike in an NMOS inverter) only one of the two transistors is driven at any one time. This means that when a CMOS inverter is not switching from one state to the other, a high impedance path exists from the supply voltage to ground, regardless of the state the inverter is in. Hence, virtually no current flows, and almost no DC power is dissipated through the CMOS inverter. CMOS thus allows the manufacture of circuits with standby power on the order of microwatts.
As device dimensions are reduced while supply voltages remain constant (or are not reduced as rapidly as the structures are scaled), the maximum electric field E
m
becomes more isolated near the drain side of the channel causing accelerated inversion-layer charges (or carriers) to enter into the overlying gate oxide. The carriers become trapped in the gate dielectric, a phenomenon generally called the hot-carrier effect. The injection of hot carriers into the gate dielectric damages the substrate/gate dielectric interface. Over time, operational characteristics of the device may degrade due to this damage, that degradation resulting in, e.g., improper variation of threshold voltage, linear region transconductance, subthreshold slope, and saturation current. This may eventually reduce the lifetime of the devices. As a result, several techniques have been developed to combat hot-carrier injection problems.
One set of methods involves making the gate dielectric and/or the gate substrate/dielectric interface more resistant to hot carriers. This may be accomplished by developing dielectric films that exhibit fewer oxide trapping centers and interface state traps. Reducing charge trapping opportunities, however, has given way to simply reducing E
m
. Reducing E
m
in the drain-side of the channel is a popular way to control the hot-carrier effect. A common approach to reducing E
m
is to minimize the abrupt voltage changes near the drain side of the channel. Disbursing abrupt voltage changes reduces E
m
strength and the harmful hot-carrier effects resulting therefrom.
Reducing E
m
occurs by replacing an abrupt drain doping profile with a more gradually varying doping profile. A more gradual doping profile distributes E
m
along a larger lateral distance so that the voltage drop is shared by the channel and the drain. Absent a gradual doping profile, an abrupt junction can exist where almost all of the voltage drop occurs across the lightly-doped channel.
The simplest method to obtain a gradual doping at the drain-side channel is to use a dopant with a high diffusivity, for example, phosphorus instead of arsenic for an n-channel device. The faster-diffusing phosphorus readily migrates from its implant position in the drain toward the channel creating a gradually doped drain and consequently a smoother voltage profile. However, the high diffusivity of phosphorus, in addition to creating a gradual lateral doping profile, also increases the lateral and vertical extents of the source and drain. Enlarging the source/drain junctions may bring about harmful short-channel effects and/or parasitic capacitances. Short-channel effects may result in less well-predicted threshold voltage, larger subthreshold currents, and altered I-V characteristics.
The most widely-used device structure for achieving a doping gradient at the drain-side of channel is the lightly-doped drain (“LDD”). An LDD structure is made by a two-step implant process. The first step takes place after the formation of the gate. For an n-channel device, a relatively light implant of phosphorus is used to form the lightly doped region adjacent the channel (i.e., the LDD implant). The LDD implants are also referred to as N
−
and P
−
implants because of their lower concentrations. A conformal CVD oxide film is then deposited over the LDD implant and interposed gate. The oxide is partially removed using an anisotropic dry-etch process. Anisotropic etch removes oxide in the substantially horizontal regions, leaving what are known as “spacers” on the sides of the gate. After the oxide spacers are formed, a second implant takes place at a higher dosage than the first implant. The second implant is chosen to use the same implant “type” (i.e., n or p) as the first. The higher concentration source/drain implant are also referred to as N
+
and P
+
implants. The source/drain implant is masked from areas adjacent the gate by virtue of the pre-existing spacers. Using an n-type example, the first implant may use phosphorus, while the second uses arsenic. The spacers serve to mask the arsenic and to offset it from the gate edges. By introducing spacers after the LDD implant, the LDD structure offers a great deal of flexibility in doping the LDD area relative to the source/drain area. The LDD area is controlled by the lateral spacer dimension and the thermal drive cycle, and is made independent from the source and drain implant (second implant) depth. The conventional LDD process, however, sacrifices some device performance to improve hot-carrier resistance. For example, the LDD process exhibits reduced drive current under comparable gate and source voltages.

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