CMOS integrated circuit and method for forming source/drain area

Details CMOS integrated circuit and method for forming source/drain area CMOS integrated circuit and method for forming source/drain area

1996-12-06

1999-02-23

Chaudhuri, Olik

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

257336, 438231, H01L 2170

Patent

active

058743430

ABSTRACT:
A transistor and a transistor fabrication method in which the heavy source/drain implants which require high-temperature thermal anneals are performed before the LDD implants which require lower temperature thermal anneals. In addition, the n-type arsenic source/drain implant which requires the highest temperature anneal is performed prior to the p-type boron implant which requires a lower temperature thermal anneal. In a conventional LDD, the LDD implants are performed first, prior to the source/drain implants. The LDD implants, especially the p-type boron implants, are annealed at a relatively low temperature. The source/drain implants require a higher thermal anneal temperature since they need to diffuse a longer distance. The n-type arsenic source/drain implants require an especially high temperature since arsenic is relatively large ion with a low diffusivity. During the high temperature thermal anneal, the LDD implants that are already present will migrate significantly. Lateral migration towards the channel will shorten the channel length and cause short-channel effects, and vertical migration into the substrate will cause an increase of the parasitic capacitance. The current invention reverses the formation process to avoid such problems. The n-type arsenic source/drain implant is performed first, and the p-type LDD implant is performed last.

REFERENCES:
patent: 5434440 (1995-07-01), Yoshitomi et al.
patent: 5491099 (1996-02-01), Hsu
patent: 5498556 (1996-03-01), Hong et al.

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