CMOS gate array with vertical transistors

Details CMOS gate array with vertical transistors CMOS gate array with vertical transistors

2001-03-14

2003-07-22

Chang, Daniel (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S101000, C326S119000

Reexamination Certificate

active

06597203

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to integrated circuits and CMOS gate arrays. In particular, the invention relates to monotonic dynamic-static pseudo-NMOS logic circuits.
BACKGROUND OF THE INVENTION
CMOS technology is used not only for digital integrated circuits due to a low power dissipation, a high density of integration and a low cost of fabrication but also for analog integrated circuits. The most important applications that are using microelectronic components, such as telecommunication equipment, industrial control equipment, auto electronics, require more and more specialized integrated circuits. The continuing development in the semiconductors has led to implementation and use of gate arrays and standard cells as the most modem and inexpensive way to produce ASIC's, Application Specific Integrated Circuits. Gate arrays technologies have a special place in the ASIC design. An ASIC is an integrated circuit that can place on a single chip an entire system or a great part of it, performing not only digital, but also analog functions. A CMOS gate array can be simply described as a matrix of pre-manufactured identical cells that only requires the addition of the final metal and contact masks to define a new circuit function. The gate array technology can quickly respond to the customer requirements in a low cost and efficient manner. Gate arrays can be implemented in a variety of circuit and process technologies including most commonly static CMOS and bipolar emitter coupled logic.
FIG. 1
shows a prior art conventional static CMOS logic circuit. There are a number of problems with static CMOS logic circuits. A first problem with static CMOS logic circuits is that each input
112
and
114
must drive two gates, the gate of one NMOS transistor and the gate of a PMOS transistor. Input
112
drives gates
116
and
118
, and input
114
drives gates
120
and
122
. This results in a large area for static CMOS circuits and a large number of metal wiring levels must be utilized to allow interconnections.
Another problem with static CMOS logic circuits is that in the PMOS transistor the hole mobility is about three times lower than the mobility of electrons if the transistors have comparable sizes. Because of this, switching transients are very asymmetrical. The charge up transient of the capacitive load in a simple inverter takes far longer than the discharge transient. To attempt to compensate, the PMOS transistors are often fabricated with a large width or size to provide symmetrical switching. However, this increases the stray capacitive loads and results in an even larger area for the circuits, and very inefficient area utilization.
A number of other approaches to overcome these shortcomings have been developed and are discussed further in the detailed description portion of the present application. However, as detailed therein, each presents or introduces new shortcomings to the circuit design.
Therefore, there is a need in the art to provide CMOS gate arrays which result in faster switching speeds, use far fewer devices to conserve chip surface space, and which require much less wiring and circuit complexity that conventional logic array approaches.
SUMMARY OF THE INVENTION
The above mentioned problems with CMOS gate arrays and other problems are addressed by the present invention and will be understood by reading and studying the following specification. Systems and methods are provided for CMOS gate arrays with vertical transistors
In one embodiment of the present invention, CMOS gate arrays with vertical transistors are used to form a logic circuit. The logic circuit includes a dynamic pull-down circuit having a number of logic inputs, a clock input, and an output. The number of logic inputs are coupled to a number of gates of free standing vertical n-channel transistors. The clock input is coupled to a gate of a free standing vertical p-channel transistor for precharging the output. The logic circuit further includes a static pull-up circuit having a number of logic inputs, a clock bar input, and an output. The number of logic inputs are coupled to a number of gates of free standing vertical n-channel transistors. The clock bar input is coupled to a gate of a free standing vertical n-channel transistor for precharging the output. And, the dynamic pull down circuit is cascaded with the static pull up circuit such that one of the number of inputs for the pull up circuit is coupled to the output of the pull down circuit.
These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims.


REFERENCES:
patent: 4797580 (1989-01-01), Sunter
patent: 5402012 (1995-03-01), Thomas
patent: 5525916 (1996-06-01), Gu et al.
patent: 5550487 (1996-08-01), Lyon
patent: 5691230 (1997-11-01), Forbes
patent: 5798938 (1998-08-01), Heikes et al.
patent: 5828234 (1998-10-01), Sprague
patent: 5867036 (1999-02-01), Rajsuman
patent: 5942917 (1999-08-01), Chappell et al.
patent: 5973514 (1999-10-01), Kuo et al.
patent: 5976282 (1999-11-01), Fukuda et al.
patent: 6040716 (2000-03-01), Bosshart
patent: 6072209 (2000-06-01), Noble et al.
patent: 6107835 (2000-08-01), Blomgren et al.
patent: 6108805 (2000-08-01), Rajsuman
patent: 6150687 (2000-11-01), Noble et al.
patent: 6174784 (2001-01-01), Forbes
patent: 6275071 (2001-08-01), Ye et al.
patent: 6304123 (2001-10-01), Bosshart
patent: 6316960 (2001-11-01), Ye
patent: 6350635 (2002-02-01), Noble et al.
patent: 6399979 (2002-06-01), Noble et al.
patent: 6476434 (2002-11-01), Noble et al.
patent: 6504201 (2003-01-01), Noble et al.
patent: 402277315 (1990-11-01), None
Wu et al., “Analysis and Design of a New Race-Free Four-Phase CMOS Logic”, Jan. 1993, IEEE Journal of Solid-State Circuits, vol. 28, No. 1, pp. 18-25.*
Bernstein, Kerry.,et al. , “High-Speed Design Styles Leverage IBM Technology Prowess”,Micro News (IBM MIcroelectronics), vol. 3, No. 4,, (1998).
Sakamoto, H..,et al. , “Grounded Load Complementary FET Circuits: Sceptre Analysis”,IEEE Journal of Solid-State Circuits, vol. SC-8, No. 4., (Aug. 1973),282-284.
Thorp, Tyler.,et al. , “Domino Logic Synthesis Using Complex Static Gates”,Proc. IEEE Conference On Computer-Aided Design, (Nov. 8-12, 1998),242-247.
Thorp, Tyler.,et al. , “Monotonic Static CMOs and Dual Vt Technology”,Int. Sym. Low Power Electronics and Design, San Diego, (Aug. 16-17, 1999), 151-155.

Affiliated with

Also associated with

Rating

CMOS gate array with vertical transistors does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with CMOS gate array with vertical transistors, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and CMOS gate array with vertical transistors will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3072523