CMOS dynamic random-access memory with active cycle one half pow

Details CMOS dynamic random-access memory with active cycle one half pow CMOS dynamic random-access memory with active cycle one half pow

1984-02-22

1986-04-22

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Precharge

365205, G11C 700

Patent

active

045846723

ABSTRACT:
A CMOS dynamic RAM is described which uses multiplexing to selectively couple two pairs of bit lines to a single sense amplifier. Both pairs of bit lines are decoupled from the sense amplifier after a word line selects a cell and before sensing occurs in the sense amplifier. Only one pair of bit lines is coupled to the input/output lines of the memory. No dummy cells are employed. The bit lines are charged to one-half the power supply potential. Restoration of potentials on each pair of bit lines occurs at different times, thereby reducing the peak currents to the RAM.

REFERENCES:
patent: 4070590 (1978-01-01), Ieda et al.
patent: 4262342 (1981-04-01), Twan
patent: 4351034 (1982-09-01), Eaton, Jr. et al.
patent: 4451906 (1984-05-01), Ikeda
D. P. Spampinato, "Differential Sense Amplifier", IBM Tech. Disclosure Bulletin, vol. 17, No. 6, Nov. 1974, pp. 1797-1798.

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