CMOS dynamic random access memory

Details CMOS dynamic random access memory CMOS dynamic random access memory

1987-11-02

1988-10-25

Moffitt, James W.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365149, 365203, 365205, 365208, G11C 700

Patent

active

047808500

ABSTRACT:
A dynamic random access memory comprises N channel sense amplifiers, P channel sense amplifiers and an equalizing MOSFET each provided for each of bit line pairs. The N channel sense amplifiers and the P channel sense amplifiers are operated by sense amplifier driving signals. In each of the N channel sense amplifiers, an MOSFET is connected between one of bit lines and an interconnection for transmitting a sense amplifier driving signal. In addition, a precharge potential generating circuit for generating a potential of (1/2)V.sub.CC is connected to the interconnection for transmitting the sense amplifier driving signal through a MOSFET. The bit line pairs are equalized by the equalizing MOSFET. Then, in each of the N channel sense amplifiers, the above described interconnection and one of the bit lines are connected to each other, and the above described interconnection and the precharge potential generating circuit are connected to each other. Therefore, the potentials on the bit line pairs and the above described interconnection are held at (1/2)V.sub.CC.

REFERENCES:
patent: 4085457 (1978-04-01), Itoh
patent: 4539658 (1985-09-01), Shimohigashi et al.
patent: 4559619 (1985-12-01), Ikeda
patent: 4564925 (1986-01-01), Onishi et al.
National Telecommunication Conference, 1982, Lecture No. 439, "Study on Sense Amplifier Driving Signal".
IEEE, ISSCC, "1 Mb CMOS DRAM with Fast Page & Static Column Modes", ISSCC 85, 1985, pp. 252-253, 2-15-85, by Shozo Saito et al.

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