CMOS device and method of manufacture

Details CMOS device and method of manufacture CMOS device and method of manufacture

2007-03-13

2007-03-13

Crane, Sara (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S635000, C257S639000, C257S640000

Reexamination Certificate

active

10826956

ABSTRACT:
A CMOS device and manufacturing method thereof wherein a bilayer etch stop is used over a PMOS transistor, and a single etch stop layer is used for an NMOS transistor, for forming contacts to the source or drain of the CMOS device. A surface tension-reducing layer is disposed between the source or drain region of the PMOS transistor and an overlying surface tension-inducing layer. The surface tension-inducing layer may comprise a nitride material or carbon-containing material, and the surface tension-reducing layer may comprise an oxide material. Degradation of hole mobility in the PMOS transistor is prevented by the use of the surface tension-reducing layer of the bilayer etch stop.

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patent: 6945838 (2005-09-01), Konishi et al.
patent: 7109568 (2006-09-01), Kumagai et al.
patent: 7115449 (2006-10-01), Yeh et al.
patent: 7118942 (2006-10-01), Li
American Heritage Dictionary, Second College Edition, 1982, p. 1223.
Hawley's Condensed Chemical Dictionary, Eleventh Edition, 1987, p. 1112.

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