CMOS circuit including double-insulated-gate field-effect...

Details CMOS circuit including double-insulated-gate field-effect... CMOS circuit including double-insulated-gate field-effect...

2007-10-16

2007-10-16

Cho, James H. (Department: 2819)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Field-effect transistor

C326S031000

Reexamination Certificate

active

11072401

ABSTRACT:
It is an object of the present invention to provide a CMOS circuit implemented using four-terminal double-insulated-gate field-effect transistors, in which the problems described above can be overcome. Another object of the present invention is to reduce power consumption in a circuit unit that is in an idle state or ready state, i.e., to reduce static power consumption. The two gate electrodes of a P-type four-terminal double-insulated-gate field-effect transistor are electrically connected to each other and are electrically connected to one of the gate electrodes of an N-type four-terminal double-insulated-gate field-effect transistor, whereby an input terminal of a CMOS circuit is formed, and a threshold voltage of the N-type four-terminal double-insulated-gate field-effect transistor is controlled by controlling a potential of the other gate of the N-type four-terminal double-insulated-gate field-effect transistor.

REFERENCES:
patent: 5466961 (1995-11-01), Kikuchi et al.
patent: 5748016 (1998-05-01), Kurosawa
patent: 6469568 (2002-10-01), Toyoyama et al.
patent: 6677803 (2004-01-01), Chiba
patent: 63-217718 (1988-09-01), None

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