CMOS buffer having stable threshold voltage

Details CMOS buffer having stable threshold voltage CMOS buffer having stable threshold voltage

1997-09-09

1999-05-04

Santamauro, Jon

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Signal level or switching threshold stabilization

326 58, 326 81, H03K 1716, H03K 190948

Patent

active

059007419

ABSTRACT:
A CMOS buffer circuit having a trip point which is insensitive to variations in temperature, supply voltages and manufacturing processes. The circuit output stage has three series-connected MOS transistors including an N channel pull-down transistor connected between the buffer output and the circuit common, a first P channel pull-up transistor connected to a positive supply voltage and a second P channel pull-up transistor connected between the first P channel transistor and the buffer output. The gates of the first P channel transistor and the N channel transistor are connected together to form the buffer input. An N channel reference transistor is used to generate a reference current which is mirrored into the output stage by a third P channel transistor which is connected to the second P channel transistor of the output stage so as to form a current mirror. Circuitry is provided to bias the reference transistor in the same manner that the N channel transistor is biased when the buffer input and output are at a predetermined trip point. Thus, the N channel transistor will cause the buffer circuit to trip at the predetermined trip point notwithstanding variations in the power supply voltage, temperature and processing.

REFERENCES:
patent: 5214320 (1993-05-01), Truong
patent: 5355033 (1994-10-01), Jang
patent: 5376843 (1994-12-01), Tien et al.
patent: 5408191 (1995-04-01), Han et al.
patent: 5428303 (1995-06-01), Pasqualini
patent: 5493235 (1996-02-01), Khayat
patent: 5668483 (1997-09-01), Roohparvar
patent: 5731713 (1998-03-01), Proebsting et al.

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