CMOS buffer circuit having power-down feature

Details CMOS buffer circuit having power-down feature CMOS buffer circuit having power-down feature

1995-08-25

1996-10-29

Westin, Edward P.

Electronic digital logic circuitry

With test facilitating feature

326112, 324158R, H03K 1920

Patent

active

055700365

ABSTRACT:
The gate of a P-channel pull-up transistor connected between an input node and a supply voltage in a buffer circuit is coupled to a test node. An N-channel pull-down transistor is connected between the input node and ground and has a gate connected to the test node. A logic low signal provided to the test node allows the circuit to operate normally. During test mode, a logic high signal is provided to the test node to turn off the P-channel pull-up transistor and thus prevent DC current flow in the circuit via the pull-up transistor. This logic high signal also turns on the pull-down transistor and, by shorting the input node to ground potential, prevents any other DC crossover currents from flowing in the circuit. Thus, during test mode, quiescent current flow resulting from small manufacturing defects in the circuit are obscured by larger DC currents and, as a result, may be readily measured to detect the presence of such small manufacturing defects.

REFERENCES:
patent: 5097206 (1992-03-01), Perner
patent: 5285119 (1994-02-01), Takahashi
patent: 5321354 (1994-06-01), Ooshima
patent: 5467026 (1995-11-01), Arnold
patent: 5469076 (1995-11-01), Badyal

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