CMOS buffer circuit having increased speed

Details CMOS buffer circuit having increased speed CMOS buffer circuit having increased speed

1995-08-25

1996-07-30

Westin, Edward P.

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Signal level or switching threshold stabilization

326121, 327537, H03K 1920

Patent

active

055415288

ABSTRACT:
A buffer circuit which exhibits increased speed in transitions between binary states. A control transistor is coupled between a pull-up transistor and an input terminal. During low-to-high input signal transitions, the control transistor limits the signal swing at the input terminal such that small variations in the input terminal voltage result in larger voltage variations at the output terminal. During such transitions, the control transistor simultaneously decouples the input terminal from the pull-up transistor, thereby decoupling the input capacitance from the pull-up transistor. As a result, the speed with which the pull-up transistor can pull the output high is increased. As the number of input signal desired to be processed increases, the reduction in logic transition time becomes more significant. Some versions further include a pull-down transistor having a control terminal coupled to the gate of the pull-up transistor and to a power-down terminal. When an appropriate voltage is applied to the power-down terminal, the pull-up transistor is turned off and the pull-down transistor is turned on such that no DC current flows in the circuit.

REFERENCES:
patent: 4874967 (1989-10-01), Deane
patent: 4920287 (1990-04-01), Hartgring
patent: 5184030 (1993-02-01), Chung
patent: 5369317 (1994-11-01), Casper
patent: 5408191 (1995-04-01), Han
patent: 5455527 (1995-10-01), Murphy

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