CMIS semiconductor nonvolatile storage circuit

Details CMIS semiconductor nonvolatile storage circuit CMIS semiconductor nonvolatile storage circuit

2007-07-24

2007-07-24

Elms, Richard T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S230080, C365S100000

Reexamination Certificate

active

11637481

ABSTRACT:
A nonvolatile semiconductor memory circuit includes a selection line, a first bit line, a second bit line, a first MIS transistor having a first gate coupled to the selection line, a first drain coupled to the first bit line via a first node, and a first source coupled to a predetermined potential, a second MIS transistor having a second gate coupled to the selection line, a second drain coupled to the second bit line via a second node, and a second source coupled to the predetermined potential, and a latch circuit coupled to the first node and the second node to store data responsive to a signal difference between the first node and the second node, wherein the selection line is operative to supply a write potential that creates a lingering change in a threshold voltage of one of the first MIS transistor and the second MIS transistor.

REFERENCES:
patent: 4578781 (1986-03-01), Ogawa et al.

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