Cluster based redundancy scheme for semiconductor memories

Static information storage and retrieval – Read/write circuit – Bad bit

Reexamination Certificate

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C365S063000

Reexamination Certificate

active

06909645

ABSTRACT:
In some embodiments, a cluster redundancy scheme may be implemented. Such a scheme may provide cluster segments including rows and columns of replacement memory elements to selectively replace defective elements arranged in rows, columns, or blocks in a main memory array of a semiconductor memory.

REFERENCES:
patent: 5519657 (1996-05-01), Arimoto
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patent: 5793683 (1998-08-01), Evans
patent: 5815449 (1998-09-01), Taura
patent: 6104648 (2000-08-01), Ooishi
patent: 6367030 (2002-04-01), Yamauchi
patent: 6522590 (2003-02-01), Matsui et al.

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