Closed-loop design for manufacturability process

Details Closed-loop design for manufacturability process Closed-loop design for manufacturability process

2006-10-31

2009-11-24

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

07624369

ABSTRACT:
A method of designing an integrated circuit is provided in which the design layout is optimized using a process model until the design constraints are satisfied by the image contours simulated by the process model. The process model used in the design phase need not be as accurate as the lithographic model used in preparing the lithographic mask layout during data prep. The resulting image contours are then included with the modified, optimized design layout to the data prep process, in which the mask layout is optimized using the lithographic process model, for example, including RET and OPC. The mask layout optimization matches the images simulated by the lithographic process model with the image contours generated during the design phase, which ensures that the design and manufacturability constraints specified by the designer are satisfied by the optimized mask layout.

REFERENCES:
patent: 6578190 (2003-06-01), Ferguson et al.
patent: 7043712 (2006-05-01), Mukherjee et al.
patent: 7100134 (2006-08-01), Wu et al.
patent: 7175940 (2007-02-01), Laidig et al.
patent: 7342646 (2008-03-01), Shi et al.
patent: 2003/0229881 (2003-12-01), White et al.
patent: 2005/0114822 (2005-05-01), Axelrad et al.
patent: 2005/0223350 (2005-10-01), Zhang et al.
patent: 2005/0229130 (2005-10-01), Wu et al.
patent: 2006/0236271 (2006-10-01), Zach
U.S. Appl. No. 11/163,264, Title: “Designer's Intent Tolerance Bands For Proximity Correction And Checking”, Date Filed Oct. 12, 2005, Applicant(s): Scott M. Mansfield, et al.
U.S. Appl. No. 11/138,172, Title: “Optical Proximity Correction Using Progressively Smoothed Mask Shapes”, Date Filed May 26, 2005, Applicant(s): Maharaj Mukherjee, et al.
Philippe Hurat, et al.—“DFM for Manufacturers and Designers”—25th Annual BACUS Symposium on Photomask Technology, Proc. of SPIE vol. 5992, (2005) pp. 59920G-1 thru 59920G-7.

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