Abrading – Abrading process – Glass or stone abrading
Reexamination Certificate
2000-07-05
2004-08-17
Hail, III, Joseph J. (Department: 3723)
Abrading
Abrading process
Glass or stone abrading
C451S005000, C451S008000, C451S011000, C451S285000, C451S286000, C451S287000, C451S288000, C451S289000
Reexamination Certificate
active
06776692
ABSTRACT:
BACKGROUND
The present invention relates generally to chemical mechanical polishing of substrates, and more particularly to closed-loop control of wafer polishing in a chemical mechanical polishing system.
Integrated circuits are typically formed on substrates, particularly silicon wafers, by the sequential deposition of conductor, semiconductor or insulator layers. After each layer is deposited, it is etched to create circuitry features. As a series of layers are sequentially deposited and etched, the outer or uppermost surface of the substrate, i.e., the exposed surface of the substrate, becomes increasingly nonplanar. This nonplanar surface presents problems in the photolithographic steps of the integrated circuit fabrication process. Therefore, there is a need to periodically planarize the substrate surface.
Chemical mechanical polishing (CMP) is one accepted method of planarization. This planarization method typically requires that the substrate be mounted on a carrier or polishing head. The exposed surface of the substrate is placed against a rotating polishing pad. The effectiveness of a CMP process can be measured by its polishing rate, and by the resulting finish (absence of small-scale roughness) and flatness (absence of large-scale topography) of the wafer surface. The polishing rate, finish and flatness are determined by the pad and slurry combination, the relative speed between the wafer and pad, and the force pressing the wafer against the pad.
A recurring problem in CMP is the “edge-effect,” in other words, the tendency of the wafer edge to be polished at a different rate than the wafer center. The edge effect typically results in non-uniform polishing at the wafer perimeter, for example, the outermost three to fifteen millimeters of a 200 millimeter (mm) wafer. A related problem is the “center slow effect,” in other words, the tendency of the center of the wafer to be underpolished.
Other factors also contribute to non-uniformity in the CMP process. For example, CMP processes are sensitive to differences among polishing pad from different lots, variations in batches of slurry, and process drifts that occur over time. In addition, CMP processes may vary with depending on environmental factors, such as temperature. The particular condition of the wafer and films deposited on the wafer also contribute to variations in the CMP process. Similarly, mechanical changes to the CMP system can affect the uniformity of the CMP process. Variations in the CMP process may occur slowly over time, for example, as a result of wear to the polishing pad. Other variations may occur as a result of a sudden change, such as when a new batch of slurry or a new polishing pad is used.
Using current techniques, it has been difficult to compensate for the foregoing variations in CMP processes to control wafer thickness dynamics. In particular, it has been difficult to control CMP processes to obtain a desired flatness or topography of the wafer surface. Similarly, it has been difficult to control CMP processes to obtain repeatable results for numerous wafers over a long period of time.
SUMMARY
In general, according to one aspect, a method of polishing a wafer uses closed-loop control. The wafer can be held by a carrier head having at least one chamber whose pressure is controlled to apply a downward force on the wafer. The method includes obtaining thickness-related measurements of the wafer and calculating a thickness profile for the wafer based on the thickness-related measurements. The calculated thickness profile is compared to a target thickness profile. The pressure in at least one carrier head chamber is adjusted based on results of the comparison.
In another implementation, a polishing method can be used with a wafer held by a carrier head having multiple chambers that can apply independently variable pressures to multiple regions of the wafer. The method includes obtaining thickness-related measurements of the wafer during polishing and adjusting a pressure in one of the carrier head chambers associated with a particular zone of the wafer based on the thickness-related measurements.
A chemical mechanical polishing system also is disclosed. The system includes a wafer polishing surface and a carrier head for holding a wafer. The carrier head includes at least one chamber whose pressure can be controlled to apply a downward pressure on the wafer as it is polished against the polishing surface. The system also has a monitor for obtaining thickness-related measurements of the wafer during polishing and memory that stores a target thickness profile. A processor is configured to: (a) calculate a thickness profile for the wafer based on a thickness-related profile obtained by the monitor; (b) compare the calculated thickness profile to a target thickness profile; and (c) adjust a pressure in at least one carrier head chamber based on results of the comparison.
In general, the chamber pressures can be adjusted in real time as a particular wafer is being polished. Thus, thickness measurements can be obtained simultaneously with polishing of the wafer, and the chamber pressure can be adjusted without removing the wafer from the polishing surface. In other implementations, thickness-related measurements of a sample wafer can be obtained and compared to the target profile so that adjustments to the chamber pressures can be made prior to or during polishing of other wafers.
In various implementations, one or more of the following features may be present. Adjusting a carrier head chamber pressure can change the pressure distribution between the wafer and a polishing surface. The carrier head can include a flexible membrane which provides a pressure to the wafer in a controllable loading area so that adjusting a chamber pressure can control the pressure applied to a wafer in the loading area. For example, if comparing the calculated thickness profile to a target thickness profile indicates that a center region of the wafer is being underpolished, then a pressure in one of the carrier head chambers can be adjusted to reduce the size of the loading area.
Similarly, adjusting a carrier head chamber pressure can change a downward force with which the wafer is pressed against the polishing surface.
Obtaining thickness-related measurements of the wafer can include measuring intensities of reflected radiation from multiple sampling zones on the wafer. The target thickness profile can represent, for example, either an ideal thickness profile or an expected thickness profile for a particular time in the polishing process.
Additionally, obtaining thickness-related measurements, calculating a thickness profile, comparing the calculated thickness profile to a target thickness profile, and adjusting a pressure in at least one of the carrier head chambers can be repeated multiple times during processing of a particular wafer.
Various implementations can include one or more of the following advantages. Variations in the wafer polishing process, such as environmental variations, variations in wafers and slurries, and variations in the CMP apparatus itself can be compensated for to provide a more uniform and more planar surface. Similarly, variations in the rate at which different regions of wafers are polished can be compensated for more easily. Although it will often be desirable to compensate for such variations so as to obtain a substantially planar surface, it may be desirable in some cases to vary the carrier head chamber pressures so that different regions of the wafer are polished to different thicknesses.
Other features and advantages will be readily apparent from the detailed description, drawings and claims.
REFERENCES:
patent: 5081796 (1992-01-01), Schultz
patent: 5486129 (1996-01-01), Sandhu et al.
patent: 5658183 (1997-08-01), Sandhu et al.
patent: 5730642 (1998-03-01), Sandhu et al.
patent: 5985094 (1999-11-01), Mosca
patent: 6159073 (2000-12-01), Wiswesser et al.
patent: 6422927 (2002-07-01), Zuniga
patent: 3801969 (1989-07-01), None
patent: 0879678 (1998-11-01), None
patent: 0904895 (1999-03-
Birang Manoocher
Zuniga Steven
Applied Materials Inc.
Fish & Richardson
Hail III Joseph J.
McDonald Sharitese
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