Clock synchronous semiconductor memory device capable of prevent

Details Clock synchronous semiconductor memory device capable of prevent Clock synchronous semiconductor memory device capable of prevent

1998-07-27

2000-04-11

Nguyen, Tan T.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365194, G11C 700

Patent

active

060494883

ABSTRACT:
A gate circuit is turned on in synchronization with an internal clock signal at a timing faster than activation of an output buffer circuit, and internal data is transmitted from the gate circuit to an output buffer circuit externally outputting data. Generation of an internal clock signal is stopped at a timing faster than deactivation of the output buffer circuit, and the gate circuit is set to the latching state. According such arrangement, output of invalid data is prevented.

REFERENCES:
patent: 5535171 (1996-07-01), Kim et al.
patent: 5557582 (1996-09-01), Kawamoto
patent: 5798969 (1998-08-01), Yoo et al.
patent: 5896323 (1999-04-01), Park et al.

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