Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses
Reexamination Certificate
2007-03-20
2007-03-20
Perveen, Rehana (Department: 2116)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
C713S375000, C713S503000
Reexamination Certificate
active
10157610
ABSTRACT:
Several algorithms are provided to estimate and remove relative clock skews from delay measurements based on the computation of convex hulls. The algorithms are linear in the number of measurement points for the case with no clock resets. For the more challenging case with clock resets, i.e., the clocks are reset to some reference times during the measurement period, linear algorithms are provided to identify the clock resets and derive the best clock skew lines. The algorithms are also extended to environments in which at least one of the clocks is controlled by Network Time Protocol. These algorithms can also be extended for active clock synchronization to replace or further improve Network Time Protocol.
REFERENCES:
patent: 6661810 (2003-12-01), Skelly et al.
Moon et al., “Estimation and Removal of Clock Skew from Network Delay Measurements”, Department of Computer Science, University of Massachusetts, 9pp.
Paxson, “On Calibrating Measurements of Packet Transit Times”, Network Research Group, University of California, Berkeley, pp. 1-13.
Liu et al. Clock Synchronization for Network Measurements, Jul. 31, 2001.
Liu Zhen
Xia Cathy Honghui
Zhang Li
Chen Tse
Glanzman Gerald H.
Perveen Rehana
Wardas Mark
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