Clock synchronization circuit

Details Clock synchronization circuit Clock synchronization circuit

2007-02-20

2007-02-20

Barnie, Rexford (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S093000, C326S094000, C326S095000, C326S097000, C326S098000, C327S141000, C327S144000, C327S145000, C327S153000

Reexamination Certificate

active

10536282

ABSTRACT:
A clock synchronization circuit for synchronizing a first clock signal and a second clock signal for data transfer from a first function block, which is clocked by the first clock signal, to a second function block which is clocked by the second clock signal, where the clock synchronization circuit has a sampling unit for sampling the second clock signal using the first clock signal in order to generate samples and edge detection values of the sampled second clock signal, a logic circuit for outputting the generated edge detection values as a reconstructed clock signal and generating an Edge-too-Early signal and an Edge-too-Late signal; and a signal delay circuit, which delays the reconstructed second clock signal on the bases of the Edge-too-Early signal or the Edge-too-Late signal.

REFERENCES:
patent: 5256912 (1993-10-01), Rios
patent: 5272391 (1993-12-01), Ampe et al.
patent: 5548620 (1996-08-01), Rogers
patent: 5638015 (1997-06-01), Gujral et al.
patent: 5654988 (1997-08-01), Heyward et al.
patent: 5721866 (1998-02-01), Ballard
patent: 5905766 (1999-05-01), Nguyen
patent: 6219395 (2001-04-01), Pollack et al.
patent: 6327207 (2001-12-01), Sluiter et al.
patent: 6359479 (2002-03-01), Oprescu
patent: 6366991 (2002-04-01), Manning
patent: 6425088 (2002-07-01), Yasukawa et al.
patent: 6744285 (2004-06-01), Mangum et al.
patent: 6988215 (2006-01-01), Splett et al.
patent: 69428071 (2002-04-01), None
patent: 1113353 (2001-07-01), None
patent: WO 01/79987 (2001-10-01), None
Semeraro et al., “Energy-Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling,”Proceedings of the Eighth International Symposium on High-Performance Computer Architecture, pp. 24-35, Feb. 2002.
German Office Action dated Sep. 11, 2003.
International Search Report dated Oct. 18, 2004 and International Preliminary Report on Patentability dated Mar. 21, 2005.

Affiliated with

Also associated with

Rating

Clock synchronization circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Clock synchronization circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Clock synchronization circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3828027