4. Multiplex communications
  5. Data flow congestion prevention or control
  6. Control of data admission to the network

Lorenzo Di Gregorio

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Clock synchronization circuit

Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
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Scheduler for signaling a time out

Multiplex communications – Data flow congestion prevention or control – Control of data admission to the network
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Scheduler for signaling a time out

Multiplex communications – Data flow congestion prevention or control – Control of data admission to the network
Reexamination Certificate

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Profile ID: LFUS-PAI-P-2348136

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