Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses
Reexamination Certificate
2007-03-13
2007-03-13
Elamin, A. (Department: 2116)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
C370S396000
Reexamination Certificate
active
10888421
ABSTRACT:
A clock synchronization backup mechanism is disclosed for maintaining clock synchronization during periods of degraded synchronization. The clock synchronization backup mechanism includes a jitter buffer having a fill value at a given sample time which is compared with a threshold. When the jitter buffer fill value exceeds the threshold, a non-normal condition is registered and the local clock frequency is set to a combination of a long-term frequency setting plus a threshold sensitive frequency adjustment. The clock synchronization backup mechanism is particularly useful for overcoming residual errors accumulated due to temperature change, oscillator degradation, and a variety of other system perturbations problematical for clock synchronization mechanisms known in the art.
REFERENCES:
patent: 6990109 (2006-01-01), Mitchell et al.
Aweya James
Markandu Jeganathan
Montuno Delfin
Ouellette Michel
Elamin A.
McGuinness & Manaras LLP
Nortel Networks Limited
Rehman Mohammed H.
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